Cortex-A65

The Cortex-A65 is a 64-bit multithreaded DynamIQ CPU.

Getting started

The Cortex-A65 is a multithreaded Cortex-A CPU. It is designed for devices undertaking high throughput and non-safety critical tasks. The Cortex-A65 is built on DynamIQ technology and benefits from its resilient and flexible multicore features.

Key Benefits

  • High throughput performance with dual-threaded, out-of-order execution.
  • Compatible with DynamIQ technology for flexible, resilient systems.
  • High bandwidth, low latency ACP interface for closely coupled accelerators.

Specifications

Architecture Armv8-A (Harvard)
 
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)

ISA support A64
Microarchitecture Pipeline Out-of-Order
  Superscalar
Yes

Neon/Floating Point Unit
Included
  Cryptography Unit
Optional

Max number of CPUs in cluster
Eight (8)
  Pysical Addressing (PA)
44-bit

Dual Core Lock-Step (DCLS)
No
Memory system and external interfaces
L1 I-Cache/D-Cache
16KB to 64KB

L2 Cache
Optional, 512KB to 4MB
  ECC Support
Yes
  LPAE Yes
  Bus interfaces
AMBA ACE or CHI
  ACP Optional
  Peripheral Port
Optional
Other Security TrustZone
  Interrupts
GIC interface, GICv4
  Generic timer Armv8-A
  PMU
PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight
CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm provides specialist code generation, debug and analysis tools for software development on Cortex-A series processors. 

    Development Tools
  • A program that is running on a desktop.
  • Learn the Armv8-A architecture

    Common to all Cortex-A series processors, these guides are useful for anyone developing assembly and C language applications for Armv8-A.

    Read the guides
  • Manual containing technical information.
  • Cortex A65 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read Here

Cortex-A comparison table (Armv7-A)
Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A
Cortex-A comparison table (Armv8-A)
Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB

L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB

L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB

ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes

LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI

ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional

Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional

Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes

Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone

Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4

Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A65 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Cortex-A65 Community Blogs

Cortex-A65 Community Forums

Suggested answer system reset request (NVIC_systemreset) does not restart the M4 controller
  • Cortex-M4
0 votes 288 views 2 replies Latest 6 hours ago by satheesh21 Answer this
Suggested answer Fixed burst and AxLEN relationship 0 votes 298 views 1 replies Latest 7 hours ago by Colin Campbell Answer this
Suggested answer Cortex-M7 (Armv7-M) Fault Question 0 votes 141 views 1 replies Latest 15 hours ago by 42Bastian Schick Answer this
Not answered 缅甸真人实体赌场18469690338 0 votes 161 views 0 replies Started 2 days ago by wns1778 Answer this
Not answered 龙虎游戏真人在线18469690338 0 votes 150 views 0 replies Started 2 days ago by wns1778 Answer this
Not answered 网上龙虎斗在线客服18469690338 0 votes 146 views 0 replies Started 2 days ago by wns1778 Answer this
Suggested answer system reset request (NVIC_systemreset) does not restart the M4 controller Latest 6 hours ago by satheesh21 2 replies 288 views
Suggested answer Fixed burst and AxLEN relationship Latest 7 hours ago by Colin Campbell 1 replies 298 views
Suggested answer Cortex-M7 (Armv7-M) Fault Question Latest 15 hours ago by 42Bastian Schick 1 replies 141 views
Not answered 缅甸真人实体赌场18469690338 Started 2 days ago by wns1778 0 replies 161 views
Not answered 龙虎游戏真人在线18469690338 Started 2 days ago by wns1778 0 replies 150 views
Not answered 网上龙虎斗在线客服18469690338 Started 2 days ago by wns1778 0 replies 146 views