Specifications

The Cortex-A65 is a multithreaded Cortex-A CPU. It is designed for devices undertaking high throughput and non-safety critical tasks. The Cortex-A65 is built on DynamIQ technology and benefits from its resilient and flexible multicore features.

Architecture Armv8-A (Harvard)
 
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)

ISA support A64
Microarchitecture





Pipeline Out-of-Order
Superscalar
Yes
Neon/Floating Point Unit
Included
Cryptography Unit
Optional
Max number of CPUs in cluster
Eight (8)
Pysical Addressing (PA)
44-bit
Dual Core Lock-Step (DCLS)
No
Memory system and external interfaces



L1 I-Cache/D-Cache
16KB to 64KB
L2 Cache
Optional, 512KB to 4MB
ECC Support
Yes
LPAE Yes
Bus interfaces
AMBA ACE or CHI
ACP Optional
Peripheral Port
Optional
Other Security TrustZone
Interrupts
GIC interface, GICv4
Generic timer Armv8-A
PMU
PMUv3
Debug Armv8-A (plus Armv8.2-A extensions)
CoreSight
CoreSightv3
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Key Benefits

  • High throughput performance with dual-threaded, out-of-order execution.
  • Compatible with DynamIQ technology for flexible, resilient systems.
  • High bandwidth, low latency ACP interface for closely coupled accelerators.