Cortex-A65

The Cortex-A65 is a 64-bit multithreaded DynamIQ CPU.

Getting started

The Cortex-A65 is a multithreaded Cortex-A CPU. It is designed for devices undertaking high throughput and non-safety critical tasks. The Cortex-A65 is built on DynamIQ technology and benefits from its resilient and flexible multicore features.

Key Benefits

  • High throughput performance with dual-threaded, out-of-order execution.
  • Compatible with DynamIQ technology for flexible, resilient systems.
  • High bandwidth, low latency ACP interface for closely coupled accelerators.

Specifications

Architecture Armv8-A (Harvard)

 

Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)
ISA support
  • A64

 

Microarchitecture Pipeline Out-of-order

 

Superscalar Yes

 

Neon/Floating Point Unit Included

 

Cryptography Unit Optional

 

Max number of CPUs in cluster Eight (8)

 

Physical Addressing (PA) 44-bit

 

Dual Core Lock-Step (DCLS) No
Memory system and external interfaces L1 I-Cache / D-Cache 16KB to 64KB

 

L2 Cache 64KB to 256KB

 

L3 Cache Optional, 512KB to 4MB

 

ECC Support Yes

 

LPAE Yes

 

Bus interfaces AMBA ACE or CHI

 

ACP Optional

 

Peripheral Port Optional
Other Security TrustZone

 

Interrupts GIC interface, GICv4

 

Generic timer Armv8-A

 

PMU PMUv3

 

Debug Armv8-A (plus Armv8.2-A extensions)

 

CoreSight CoreSightv3

 

Embedded Trace Macrocell ETMv4.2 (instruction trace)

Resources

Cortex-A Series Programmer's Guide for Armv8-A

Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

Development Tools for Cortex-A

Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as Arm Development Studio.

Use Arm models for Cortex-A65 performance evaluation, early software development and software validation farms.


Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A65 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Cortex-A65 Community Blogs

Cortex-A65 Community Forums

Not answered Cortex A9 Coresight TMC configuration 0 votes 21 views 0 replies Started 10 hours ago by Jan VdH Answer this
Suggested answer For Armv8-M, is there a system register indicating the security state of the core? 0 votes 49 views 1 replies Latest 13 hours ago by 42Bastian Schick Answer this
Answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? 0 votes 265 views 3 replies Latest 14 hours ago by jpthibault Answer this
Answered Cortex-A53 processor instruction cycles
  • cycle
  • Cortex-A53
  • Cortex-A
0 votes 5167 views 8 replies Latest 15 hours ago by 42Bastian Schick Answer this
Suggested answer What options do I have for a GUI and an LCD? 0 votes 147 views 3 replies Latest 17 hours ago by 42Bastian Schick Answer this
Suggested answer Relocating the Vector table in Cortex - M0 0 votes 267 views 5 replies Latest yesterday by Joseph Yiu Answer this
Not answered Cortex A9 Coresight TMC configuration Started 10 hours ago by Jan VdH 0 replies 21 views
Suggested answer For Armv8-M, is there a system register indicating the security state of the core? Latest 13 hours ago by 42Bastian Schick 1 replies 49 views
Answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? Latest 14 hours ago by jpthibault 3 replies 265 views
Answered Cortex-A53 processor instruction cycles Latest 15 hours ago by 42Bastian Schick 8 replies 5167 views
Suggested answer What options do I have for a GUI and an LCD? Latest 17 hours ago by 42Bastian Schick 3 replies 147 views
Suggested answer Relocating the Vector table in Cortex - M0 Latest yesterday by Joseph Yiu 5 replies 267 views