A 64-bit multi-threaded CPU with Split-Lock capability for functional safety.

The Cortex-A65AE is the first multi-threaded Cortex-A CPU for automotive applications. It is designed for devices undertaking high throughput and safety critical tasks. The Cortex-A65AE is built on DynamIQ technology and benefits from its resilient and flexible multicore features. It has also been designed with Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs.

The Cortex-A65AE is part of the Arm Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.

Architecture Armv8-A (Harvard)
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)

ISA support A64  
Pipeline Out-of-order
Superscalar Yes
Neon / floating point unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
Physical Addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache / D-Cache 32KB to 64KB
L2 Cache 64KB to 256KB
L3 Cache Optional, 512KB to 4MB
ECC Support Yes
Bus interfaces AMBA ACE or CHI
ACP Optional
Peripheral Port Optional
Functional safety

Dual Core Lock-Step Yes (in Lock-mode)
Memory protection Yes
Interface protection Yes
Safety capability
  • Contributes up to ASIL D hardware diagnostic metrics
  • Suitable for up to ASIL D systematic development
Safety package Yes (Extended Package)

Functional Safety Support Supports ASIL D diagnostics
Security TrustZone
Interrupts GIC interface, GICv4
Generic timer Armv8-A
Debug Armv8-A (plus Armv8.2-A extensions)
CoreSight CoreSightv3
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Arm Security Algorithm Accelerators

Download the hardware block:

Cortex-A65AE_Security_Algorithm_Accelerator.tar.gz 465 KB

Key benefits

  • High throughput performance with dual-threaded, out-of-order execution
  • Split-Lock capability which offers the flexibility to operate in two modes; split mode for performance and lock mode for safety.
  • Fault-tolerant operation in lock mode with DCLS.

Key benefits compared to Cortex-A53 (at iso-frequency):

  • 80% improved integer performance per core
  • 3.5x higher memory throughput for memory intensive automotive workloads
  • 6x higher in Machine Learning performance
  • >6x higher read bandwidth on low-latency ACP for closely-coupled accelerators