A 64-bit multi-threaded CPU with Split-Lock capability for functional safety.
The Cortex-A65AE is the first multi-threaded Cortex-A CPU for automotive applications. It is designed for devices undertaking high throughput and safety critical tasks. The Cortex-A65AE is built on DynamIQ technology and benefits from its resilient and flexible multicore features. It has also been designed with Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs.
The Cortex-A65AE is part of the Arm Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.
|Neon / floating point unit||Included|
|Max number of CPUs in cluster||Eight (8)|
|Physical Addressing (PA)||44-bit|
|Memory system and external interfaces||L1 I-Cache / D-Cache||32KB to 64KB|
|L2 Cache||64KB to 256KB|
|L3 Cache||Optional, 512KB to 4MB|
|Bus interfaces||AMBA ACE or CHI|
||Dual Core Lock-Step||Yes (in Lock-mode)|
|Safety package||Yes (Extended Package)|
||Functional Safety Support||Supports ASIL D diagnostics|
|Interrupts||GIC interface, GICv4|
|Debug||Armv8-A (plus Armv8.2-A extensions)|
|Embedded Trace Macrocell||ETMv4.2 (instruction trace)|
- High throughput performance with dual-threaded, out-of-order execution
- Split-Lock capability which offers the flexibility to operate in two modes; split mode for performance and lock mode for safety.
- Fault-tolerant operation in lock mode with DCLS.
Key benefits compared to Cortex-A53 (at iso-frequency):
- 80% improved integer performance per core
- 3.5x higher memory throughput for memory intensive automotive workloads
- 6x higher in Machine Learning performance
- >6x higher read bandwidth on low-latency ACP for closely-coupled accelerators
Cortex-A comparison table for Armv7-A and Armv8-A
Download the following PDF datasheet to compare the specifications of Cortex-A Armv7-A and Armv8-A processors.