Cortex-A7

The Arm Cortex-A7 processor is the most efficient Armv7-A processor.

Information on Cortex-A7.

Getting Started

The Cortex-A7 processor provides up to 20% more single thread performance than the Cortex-A5. The processor incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including virtualization support in hardware, Large Physical Address Extensions (LPAE), Neon, and 128-bit AMBA 4 AXI bus interface.


Specifications

Architecture Armv7-A
Multicore 1-4 cores. Symmetric Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
ISA Support
  • Armv7-A
  • Thumb-2
  • TrustZone security technology
  • DSP extensions
  • Neon advanced SIMD
  • VFPv4 Floating Point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
Memory Management Unit (MMU)
Armv7 Memory Management Unit
Debug & Trace
CoreSight

Characteristics

The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this there is improved branch prediction and an improved memory system performance, with 64-bit load-store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web browsing.

In a 28nm process, the Cortex-A7 can run at 1.2-1.6GHz, has an area of 0.45mm2 (with Floating-Point Unit, Neon and a 32KB L1 cache) and requires less than 100mW of total power in typical conditions. This lowest performance profile makes it an ideal standalone processor for a range of mobile devices, and means the Cortex-A7 can ultimately deliver similar performance to the Cortex-A9 processor at much higher levels of power efficiency.


  • Manual containing technical information.
  • Cortex-A7 Technical Reference Manual

    For system designers and software engineers, the Cortex-A7 manual provides information on implementing and programming Cortex-A7 based devices.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the Guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio

    Development Tools

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode)
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A7 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A7 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali GPUs

Mali Display Processors

Mali-V500 Video Processor

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

Community Blogs

Community Forums

Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state?
  • Armv8-A
  • AArch32
0 votes 58 views 1 replies Latest 14 hours ago by 42Bastian Schick Answer this
Suggested answer How to Change the Non Secure VTOR (Cortex-M33)
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Suggested answer How to import C variable in an assembly code in a .s file
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Answered Watchdog timer not entering ISR
  • Cortex-A9
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  • Cortex-A
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0 votes 102 views 2 replies Latest yesterday by sherry Answer this
Not answered Dual core cortex-m7 for security applications
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0 votes 39 views 0 replies Started yesterday by Haram80 Answer this
Not answered Trigger a Software Interrupt
  • STM32
  • Cortex-M
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  • Interrupt
0 votes 44 views 0 replies Started 2 days ago by Aquox Answer this
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state? Latest 14 hours ago by 42Bastian Schick 1 replies 58 views
Suggested answer How to Change the Non Secure VTOR (Cortex-M33) Latest yesterday by 42Bastian Schick 1 replies 85 views
Suggested answer How to import C variable in an assembly code in a .s file Latest yesterday by Georgia James 1 replies 61 views
Answered Watchdog timer not entering ISR Latest yesterday by sherry 2 replies 102 views
Not answered Dual core cortex-m7 for security applications Started yesterday by Haram80 0 replies 39 views
Not answered Trigger a Software Interrupt Started 2 days ago by Aquox 0 replies 44 views