Cortex-A72

The Cortex-A72 processor is an efficient high-performance processor that implements the Armv8-A architecture.

Information on arm Cortex-A72.

Getting Started

The Cortex-A72 processor can be paired with the Cortex-A53 processor in a big.LITTLE configuration for mobile applications. The Cortex-A72 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.

Contact Us

Specifications

Architecture  Armv8-A
 Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
 ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • Neon advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
 Debug & Trace
  • A guide on software optimization.

  • Cortex-A72 Software Optimization Guide

    For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.

    Get the guide
  • Manual containing technical information.

  • Cortex-A72 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • Architecture A 62 guide

  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.

  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • A program that is running on a desktop.

  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • A manual that contains information on safety.

  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

  • Laptop, tablet, mobile phone etc.

  • High Performance Computing for Cortex-A72

    Watch this webinar to learn how the Arm Cortex-A72 processor can help High Performance Computing use cases.

    Watch now

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB		 NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3		 External
GICv3		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv4		 External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A72 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A72 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A72 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
 Other IP
 Tools

Arm Mali-T860 and Mali-T880 (GPU)

 

 

CoreLink Cache Coherent Interconnect Family

CoreLink System Controllers

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

Arm POP (Physical IP)

Arm Development Studio

Fixed Virtual Platforms

Arm Versatile Express

Arm Compiler 6

Arm Fast Models

Community Blogs

Blog post image
Deploy State-of-the-Art Deep Learning on Edge Devices in Minutes

Deploying advanced deep learning algorithms on edge devices, especially for computer vision applications like autonomous vehicles and IoT, requires special capabilities.

1 years ago by Amir Alush
1
Blog post image
Security, the Fundamental Element in Next-Generation Networks

This blog will focus on some of the key technologies needed to protect network access, availability and data, with a brief overview of Arm’s underlying platform that is providing the foundation for trust.

1 years ago by Jim Wallace
1
Blog post image
Arm partnership providing the foundation for next generation networks

Service providers or anyone involved in building out next-generation networks are faced with complex challenges today as they seek to evolve, future-proof, and secure their networks to meet the ever-increasing needs of our hyper connected world.

1 years ago by Jim Wallace
Blog post image
What Arm Achieved by Graduating to a Formal Sign-Off Methodology

Arm’s use of Formal verification sign-off on Cortex-A designs proved successful but lessons were still learned on how to strengthen its Formal strategy.

1 years ago by Rob van Blommestein
1
Blog post image
Arm Ecosystem rolls into SDN World Congress with a new uCPE Reference Platf

It’s not easy to stay competitive in today’s fast-moving service provider market. Telcos and managed service providers need every edge they can get.

1 years ago by Bob Monkman
Blog post image
What's next for voice in the car? A Q&A with ARM & Recognition

Soshun Arai, Arm and Mark Sykes, Recognition Technologies discuss the next generation of embedded voice for the automotive cockpit. Recognition Technologies is a partner of Arm and their RecoMadeEasy® software provides embedded natural language s

2 years ago by Eoin McCann

Community Forums

Suggested answer Cortex-R5: Divide-by-zero
  • Armv7 Exception Model
  • Cortex-R5
  • Processors
  • Software Development
 0 votes 260 views 2 replies Latest 9 hours ago by Tau Answer this
Answered How to specify virtual Address for pl011 uart in linux kernel
  • APB Peripherals
  • Arm11
  • PrimeCell UART (PL011)
  • Interrupt
 0 votes 4138 views 6 replies Latest 3 days ago by smithclarkson01 Answer this
Suggested answer Program Counter, Stack Pointer and Link Register Status During an Interrupt Service in ARM based Processors 0 votes 180 views 2 replies Latest 4 days ago by Aman007kc Answer this
Suggested answer ARM Assembly how to print numbers instead of their ascii representation of that number
  • Armv6
  • Arm Assembly Language (ASM)
 0 votes 281 views 2 replies Latest 4 days ago by Kanan Jarrus Answer this
Not answered Why there is no translation tables concatenation for stage 1 of VA translation? 0 votes 67 views 0 replies Started 5 days ago by Uzi Shvadron Answer this
Suggested answer Cortex R8 axi unaligned transfer
  • program
  • cortex-r8
 0 votes 333 views 2 replies Latest 5 days ago by Ben Chen Answer this
Suggested answer Cortex-R5: Divide-by-zero Latest 9 hours ago by Tau 2 replies 260 views
Answered How to specify virtual Address for pl011 uart in linux kernel Latest 3 days ago by smithclarkson01 6 replies 4138 views
Suggested answer Program Counter, Stack Pointer and Link Register Status During an Interrupt Service in ARM based Processors Latest 4 days ago by Aman007kc 2 replies 180 views
Suggested answer ARM Assembly how to print numbers instead of their ascii representation of that number Latest 4 days ago by Kanan Jarrus 2 replies 281 views
Not answered Why there is no translation tables concatenation for stage 1 of VA translation? Started 5 days ago by Uzi Shvadron 0 replies 67 views
Suggested answer Cortex R8 axi unaligned transfer Latest 5 days ago by Ben Chen 2 replies 333 views