The Cortex-A73 processor is a highly-efficient high-performance processor.

The Cortex-A73 processor can be paired with the Cortex-A53 or Cortex-A35 processor in a big.LITTLE configuration for an array of mobile and embedded devices. The Cortex-A73 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.

Information on Cortex-A73.

Arm Cortex-A73 CPU

Architecture  Armv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology
ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • Neon advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
Debug & Trace

Arm Security Algorithm Accelerators

Download the hardware block:

Cortex-A73_Security_Algorithm_Accelerator.tar.gz 615 KB

Key features

Efficient Out-of-Order Pipeline
Microarchitecture performance and power improvements to maximize efficiency of the 2-wide out-of-order pipeline. High and sustained performance at frequencies up to 2.8GHz in advanced process technology for premium smartphones.

State-of-the-art Branch Prediction and Power-Optimized Instruction Fetching
Advanced sophisticated prediction algorithm with power-optimized 64kB instruction cache.

High-performance Memory System
Full out-of-order dual-issue load/store capability combined with up to 64kB data cache. Enhanced data prefetching with automatic complex pattern detection.

Optimized mobile and consumer feature set
Combined with Cortex-A53 or Cortex-35 in big.LITTLE configuration using Arm CCI interconnect for high scalability.