The Arm Cortex-A75 processor is a high performance application CPU delivering high performance and power efficiency across a wide range of applications. 

First-generation CPU built on DynamIQ technology, enabling high levels of scalability and responsiveness for advanced use cases. 

The processor is broadly applicable from cloud to edge, providing improvements in performance, efficiency, and architecture over its predecessors. With significantly improved integer performance, and substantial enhancements in floating point and memory workloads performance, the Cortex-A75 processor provides a suitable solution for an array of devices. 

This additional compute capability, combined with improvements for machine learning and other advanced use cases, will enable demanding applications to run more smoothly.

Information on Cortex-A75.

Arm Cortex-A75 CPU

Architecture Armv8-A (Harvard)
Armv8.1 extensions,
Armv8.2 extensions,
Cryptography extensions,
RAS extensions,
Armv8.3 (LDAPR instructions only)

ISA support
A64, A32, and T32 instruction sets

Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon / Floating Point Unit  Included
Cryptography Unit
Max Number of CPUs in Cluster Four (4)
Physical Addressing (PA) 44-bit
Memory System and External Interfaces L1 I-Cache / D-Cache 64KB
L2 Cache 128KB to 512KB 
L3 Cache Optional 512KB to 4MB
ECC Support Yes 
Bus Interfaces ACE or CHI 
ACP Optional 
Peripheral Port Optional 
Other Functional Safety Support Safety package
Security TrustZone 
Interrupts GIC Interface, GICv4 
Generic Timer  Armv8-A
Debug Armv8-A (plus Armv8.2-A extensions) 
CoreSight CoreSightv3 
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Arm Security Algorithm Accelerators

Download the hardware block:

Cortex-A75_Security_Algorithm_Accelerator.tar.gz 518 KB