Cortex-A76

The Arm Cortex-A76 CPU delivers laptop-class performance with smartphone efficiency, bringing the same experience to all classes of intelligent mobile compute devices.

Information on Cortex-A76.

Getting Started

The Arm Cortex-A76 CPU is the second generation premium core built on DynamIQ technology. Paired with a Cortex-A55 CPU in a scalable DynamIQ big.LITTLE configuration, the Cortex-A76 delivers laptop-class performance with mobile efficiency, bringing the mobile experience (fast responsiveness, always on, always connected) into all classes of intelligent mobile compute devices. With superior energy efficiency and far greater single-threaded performance, the Cortex-A76 CPU extends battery life and improves user experience for sustained high performance across even the most complex compute tasks.

Key benefits

  • Better experience, user responsiveness, new ML/AI applications and virtual experiences.
  • Brings the always-on functionality of mobile to large screen devices, extending battery life for longer experiences.
  • 4x performance for inference ML at the edge.

Key features compared to Cortex-A75

  • 40% better power efficiency.
  • 35% improved performance.
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Specifications

Architecture Armv8-A (Harvard)  
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)
ISA support
  • A64
  • A32 and T32 (at the EL0 only)
  
Microarchitecture Pipeline Out-of-order
  Superscalar Yes
  Neon / Floating Point Unit Included
  Cryptography Unit Optional
  Max number of CPUs in cluster Four (4)
  Physical addressing (PA) 40-bit
Memory system and external interfaces L1 I-Cache / D-Cache 64KB
  L2 Cache 128KB to 512KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  LPAE Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support ASIL D systematic
  Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)
  • A program that is running on a desktop.

  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • a ulink, a board, a desktop.

  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as Arm Development Studio

    Development Tools

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB		 NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3		 External
GICv3		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv4		 External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A76 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Blog post image
Bringing Armv8.2 Instructions to Android Runtime

Arm Architecture v8.2 features were detailed in 2016. Just two years later, in 2018, flagship Android phones with ARMv8.2 features (Google Pixel3, Huawei Mate 20 Pro, Samsung Galaxy S9, etc) started shipping in volume.

4 months ago by Xueliang Zhong
2
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ARM编译器6.11的新功能

在2018年10月底发布的arm Compiler 6.11实现了一个新的里程碑。 arm Compiler 6.11的主要亮点是： 在Cortex-M33上获得最佳CoreMark分数:3.96 CoreMarks / MHz。 支持最新的arm架构扩展。 在一些重要嵌入式工作负载上的性能改进。 增加对C ++ 14的支持。 arm新架构的早期支持 arm Compiler一直处于支持新架构和新内核的前沿，因此arm Compiler 6.11版本在汇编器中增加了armv8.5-A架构支持

6 months ago by 章政
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Arm Compiler 6.11 – What’s New?

Another milestone achieved for the Arm Compiler 6.11.

6 months ago by Peterson Quadros
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How machine learning at the edge is helping to save Rudolph this Christmas

This blog provides details about how machine learning at the edge is helping to save reindeer this Christmas through a reindeer cam that alerts train drivers when reindeer stray onto the train lines in Norway.

7 months ago by Jack Melling
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Keeping up with the Cadence: Accelerating Implementation with POP IP

Arm POP IP adds value in four key ways, helping you keep up with the cadence and bring the latest Arm processor cores to market.

7 months ago by Kelvin Low
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How Arm, Microsoft and Qualcomm are revolutionizing the PC experience

A summary of the key discussion points from the 'Revolutionizing the PC experience' Tech Panel at TechCon with representatives from Arm, Microsoft and Qualcomm.

8 months ago by Mitesh Soni

Community Forums

Answered Cycle count for a subroutine on Cortex M33 0 votes 223 views 2 replies Latest 2 days ago by Ed Player Answer this
Answered Where to find hard core Arm books, courses, tutorials
  • Arm7tdmi
 0 votes 2190 views 6 replies Latest 3 days ago by drake00 Answer this
Answered Debug Unit Cortex - R 0 votes 346 views 3 replies Latest 5 days ago by Martin Weidmann Answer this
Answered Disable data prefetching in a Cortex-A53 running Android
  • Cortex-A53
  • EL1
  • L1
  • L2
 0 votes 945 views 6 replies Latest 9 days ago by DNovo Answer this
Answered How to determine which core is generating the AXI read transaction in a multi core processor?
  • Cortex-A72
 0 votes 697 views 3 replies Latest 9 days ago by MNB Answer this
Answered ARM Cortex A5 -Issue: Undefined Instruction when write/read value of CNTFRQ register in core ARMv7 0 votes 646 views 2 replies Latest 10 days ago by Khuong Nguyen Answer this
Answered Cycle count for a subroutine on Cortex M33 Latest 2 days ago by Ed Player 2 replies 223 views
Answered Where to find hard core Arm books, courses, tutorials Latest 3 days ago by drake00 6 replies 2190 views
Answered Debug Unit Cortex - R Latest 5 days ago by Martin Weidmann 3 replies 346 views
Answered Disable data prefetching in a Cortex-A53 running Android Latest 9 days ago by DNovo 6 replies 945 views
Answered How to determine which core is generating the AXI read transaction in a multi core processor? Latest 9 days ago by MNB 3 replies 697 views
Answered ARM Cortex A5 -Issue: Undefined Instruction when write/read value of CNTFRQ register in core ARMv7 Latest 10 days ago by Khuong Nguyen 2 replies 646 views