This processor is based on the second generation DynamIQ CPU, Cortex-A76 and comes with Split-Lock capability which includes Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs.

The Cortex-A76AE is the first of an all new Arm Cortex-A family of high performance processors for the emerging smart automotive market and it is designed for devices undertaking complex and demanding safety critical tasks.

The Cortex-A76AE is part of the Arm Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.

Cotex-A76AE Block Diagram
Architecture Armv8-A (Harvard)  
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)

ISA support
  • A64
  • A32 and T32 (at the EL0 only)
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon / Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Four (4)
Physical Addressing (PA) 40-bit
Memory system and external interfaces L1 I-Cache / D-Cache 64KB
L2 Cache 128KB to 512KB
L3 Cache Optional, 512KB to 4MB
ECC Support Yes
Bus interfaces AMBA ACE or CHI
ACP Optional
Peripheral Port Optional
Functional Safety

Dual Core Lock-Step (DCLS) Yes (in safety-mode)
Memory protection Yes
Interface protection Yes
Safety capability
  • Contributes towards up to ASIL D hardware diagnostic metrics.
  • Suitable for up to ASIL D systematic development
Safety package Yes (Extended package)
Other Functional Safety Support Supports ASIL D diagnostics
Security TrustZone
Interrupts GIC interface, GICv4
Generic timer Armv8-A
Debug Armv8-A (plus Armv8.2-A extensions)
CoreSight CoreSightv3
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Arm Security Algorithm Accelerators

Download the hardware block:

Cortex-A76AE_Security_Algorithm_Accelerator.tar.gz 592 KB

Key benefits

  • Split-Lock capability which offers the flexibility to operate in two modes; split mode for performance and lock mode for safety.
  • Fault-tolerant operation in lock mode with DCLS.
  • 4x performance for inference machine learning at the edge.

Key features compared to Cortex-A75

  • 40% better power efficiency per core.
  • 35% improved performance per core.