Cortex-A77

Delivering premium performance with best-in-class power efficiency to mobile and laptop devices in a soon to be 5G connected world. 

Arm Cortex-A77 Block Diagram

Getting started

The Arm Cortex-A77 CPU is the third-generation premium core built on DynamIQ technology. It can be paired with Cortex-A55 CPUs in a scalable DynamIQ big.LITTLE configuration. Cortex-A77 delivers higher performance with greater efficiency to all mobile and laptop devices. Consumers are now demanding greater performance from their devices along with multi day battery life. Cortex-A77 enables the end user to enjoy sustained high performance across even the most complex compute tasks in a soon to be 5G connected world. Building on the best-in-class power and area efficiency originally established with previous generations of Cortex-A processors.

Key Benefits

  • Improved performance for mobile and laptop devices enabling more immersive AAA-gaming, faster web-browsing and application launch time.
  • Brings an improved always-on, always-connected feature set of mobile to laptop devices, extending battery life for a charger-less work day.
  • Aligned with Arm's premium solutions such as Mali-G77, and Arm's machine learning (ML) processor.

Key features compared to Cortex-A76

  • Up to 20% improved IPC performance from mobile to laptop devices.
  • Improved user experience with more performance through major micro-architectural updates.
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Specifications

 Architecture  Armv8-A (Harvard)  
 Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
 Armv8.3 (LDAPR instructions only)
 
 ISA support
  • A64
  • A32 and T32 (at the EL0 only) 
 
 Microarchitecture
 Pipeline  Out-of-order
   Superscalar
 Yes
   Neon / Floating Point Unit  Included
   Cryptography Unit
 Optional
   Max number of CPUs in cluster
 Four (4)
   Physical Addressing (PA)  40-bit
 Memory system and external interfaces
 L1 I-Cache / D-Cache  64KB
   L2 Cache  256KB to 512KB
   L3 Cache  Optional, 512KB to 4MB
   ECC Support  Yes
   LPAE  Yes
   Bus interfaces             AMBA ACE or CHI
   ACP  Optional
   Peripheral Port  Optional
   Functional Safety Support  ASIL D systematic
   Security  TrustZone
   Interrupts  GIC interface, GICv4
   Generic timer  Armv8-A
   PMU  PMUv3
   Debug  Armv8-A (plus Armv8.2-A extensions)
   CoreSight  CoreSightv3
   Embedded Trace Macrocell  ETMv4.2 (instruction trace)


  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A Processors

    Arm provides specialist code generation, debug and analysis tools for software development on Cortex-A series processors. 

    Development Tools

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A77 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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Community Forums

Suggested answer Relocating the Vector table in Cortex - M0 0 votes 166 views 5 replies Latest 5 hours ago by Joseph Yiu Answer this
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware 0 votes 3577 views 9 replies Latest 11 hours ago by MSK Answer this
Suggested answer What options do I have for a GUI and an LCD? 0 votes 85 views 1 replies Latest 17 hours ago by Joseph Yiu Answer this
Discussion 4-kbyte boundary space 0 votes 9763 views 10 replies Latest yesterday by Colin Campbell Answer this
Suggested answer Timer0 do not count at the theoretical frequency 0 votes 78 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Answered Disable data prefetching in a Cortex-A53 running Android
  • Cortex-A53
  • el1
  • l1
  • l2
0 votes 206 views 3 replies Latest yesterday by vstehle Answer this
Suggested answer Relocating the Vector table in Cortex - M0 Latest 5 hours ago by Joseph Yiu 5 replies 166 views
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware Latest 11 hours ago by MSK 9 replies 3577 views
Suggested answer What options do I have for a GUI and an LCD? Latest 17 hours ago by Joseph Yiu 1 replies 85 views
Discussion 4-kbyte boundary space Latest yesterday by Colin Campbell 10 replies 9763 views
Suggested answer Timer0 do not count at the theoretical frequency Latest yesterday by 42Bastian Schick 1 replies 78 views
Answered Disable data prefetching in a Cortex-A53 running Android Latest yesterday by vstehle 3 replies 206 views