The Cortex-A78C CPU provides a scalable solution with advanced security features and large big-core configurations.

The Cortex-A78C CPU is built on the foundation of the Cortex-A78 CPU as part of a scalable solution with advanced security and architecture features allowing up to eight big-core-only CPU configurations. Along with this enhanced CPU configuration, the Cortex-A78C also includes memory system improvements allowing up to 8MB of shared L3 Cache for demanding workloads, including AAA gaming, multimedia editing and other professional productivity suites.

Arm Cortex-A78C block diagram

Arm Cortex-A78C CPU

Architecture Armv8-A (Harvard)  
  • Armv8.1 extensions

  • Armv8.2 extensions

  • Cryptography extensions

  • RAS extensions

  • Armv8.3-A LDAPR instructions

  • Armv8.3-A Pointer Authentication support

  • Armv8.6-A Enhanced Pointer Authentication support (excluding the optional FPAC extension)

  • Armv8.4 multi-OS support

ISA support
  • A64
  • A32 and T32 (at the EL0 only) 
Pipeline Out of order
Neon / Floating Point Unit Included
Cryptography Unit
Max number of CPUs in cluster
Eight (8)
Physical Addressing (PA) 40-bit
Memory system and external interfaces
L1 I-Cache / D-Cache 32KB or 64KB
L2 Cache 256KB to 512KB
L3 Cache Optional, 512KB to 8MB
ECC Support Yes
Bus interfaces            AMBA ACE or CHI
ACP Optional
Peripheral Port Optional
Functional Safety Support ASIL D systematic
Security TrustZone
Interrupts GIC interface, GICv4
Generic timer Armv8-A
Debug Armv8-A (plus Armv8.2-A extensions)
CoreSight CoreSightv3
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Arm Security Algorithm Accelerators

Download the hardware block:

Cortex-A78C_Security_Algorithm_Accelerator.tar.gz 586 KB

Key features compared to Cortex-A78

  • DynamIQ Shared Unit allows up to eight big-core-only configurations in one cluster, with up to 8MB L3 cache.
  • Pointer Authentication significantly reduces exploits and prevents attackers from taking control of the software control flow.