Cortex-A78C | Community – Arm Developer

Blog posts

Time to get excited about the growing Windows on Arm Ecosystem

This blog highlights the latest developments with the growing Windows on Arm ecosystem.

Parallel heterogenous computing for IoT-boards and nanocomputers with Armv8…

Read this guest blog by Arthur Ratz about computing for IoT-boards and nanocomputers with Armv8-A and AArch64. This is a guest blog contribution from Arthur Ratz Build and run a modern parallel code in C++17 and CL and SYCL programming model…

11 days ago by Arthur Ratz

Memory Model Tool: Morello (and some Memory Tagging)

This post presents a new extension to the Memory Model Tool: the implementation of the Morello architectural features.

26 days ago by Ambroise Vincent

Accelerating Edge Computing with Arm Ethos-N78 and Artisan Physical IP on…

In this blog, read about how to accelerate Edge Computing with Arm Ethos-N78 and Artisan.

27 days ago by Lakshmi Jain

Arm Cortex-A78C CPU: Secure and scalable performance for next-generation…

This blog provides details about key features and benefits of the Arm Cortex-A78C CPU, which is the latest addition to the Cortex-A78 family.

29 days ago by Vincent Risson

Expanding the Memory Model Tools to System-level architecture

Memory Model Tools: System-level architecture. In this blog, learn about how to run System-level litmus tests using KVM.

1 months ago by Jade Alglave

Popular forum posts

Answered	Is it possible to enable or disable the nested interrupt mechanism on M0 ?	0 votes	147 views	2 replies	Latest 5 days ago by Robert McNamara	Answer this
Answered	How long are the Cortex-M7 pipeline stages? Cortex-M7 Cortex-M	0 votes	28376 views	18 replies	Latest 8 days ago by Pacocha	Answer this
Answered	Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1? AArch64 Armv8-A AArch32	0 votes	2015 views	2 replies	Latest 8 days ago by George_	Answer this
Answered	Disable Cache L1 et L2 Armv8 Cortex-A72 Cache Armv8-A	1 votes	2516 views	7 replies	Latest 12 days ago by 42Bastian Schick	Answer this
Answered	Is Advanced-SIMD supported in Cortex-R5F? Cortex-R Cortex-R5 Armv7-R SIMD and Vector Execution	0 votes	4533 views	4 replies	Latest 15 days ago by Koppu	Answer this
Answered	Cortex-A7 pipeline is non-symmetric, what does this attribute mean? Cortex-A53 Cortex-A15 Cortex-A Cortex-A7	0 votes	10055 views	10 replies	Latest 15 days ago by Jerome Decamps - 杜尚杰	Answer this

Answered	Is it possible to enable or disable the nested interrupt mechanism on M0 ? Latest 5 days ago by Robert McNamara	2 replies 147 views
Answered	How long are the Cortex-M7 pipeline stages? Latest 8 days ago by Pacocha	18 replies 28376 views
Answered	Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1? Latest 8 days ago by George_	2 replies 2015 views
Answered	Disable Cache L1 et L2 Armv8 Latest 12 days ago by 42Bastian Schick	7 replies 2516 views
Answered	Is Advanced-SIMD supported in Cortex-R5F? Latest 15 days ago by Koppu	4 replies 4533 views
Answered	Cortex-A7 pipeline is non-symmetric, what does this attribute mean? Latest 15 days ago by Jerome Decamps - 杜尚杰	10 replies 10055 views