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Answered Is it possible to enable or disable the nested interrupt mechanism on M0 ? 0 votes 147 views 2 replies Latest 5 days ago by Robert McNamara Answer this
Answered How long are the Cortex-M7 pipeline stages?
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  • Cortex-M
0 votes 28376 views 18 replies Latest 8 days ago by Pacocha Answer this
Answered Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
  • AArch64
  • Armv8-A
  • AArch32
0 votes 2015 views 2 replies Latest 8 days ago by George_ Answer this
Answered Disable Cache L1 et L2 Armv8
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  • Cache
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1 votes 2516 views 7 replies Latest 12 days ago by 42Bastian Schick Answer this
Answered Is Advanced-SIMD supported in Cortex-R5F?
  • Cortex-R
  • Cortex-R5
  • Armv7-R
  • SIMD and Vector Execution
0 votes 4533 views 4 replies Latest 15 days ago by Koppu Answer this
Answered Cortex-A7 pipeline is non-symmetric, what does this attribute mean?
  • Cortex-A53
  • Cortex-A15
  • Cortex-A
  • Cortex-A7
0 votes 10055 views 10 replies Latest 15 days ago by Jerome Decamps - 杜尚杰 Answer this
Answered Is it possible to enable or disable the nested interrupt mechanism on M0 ? Latest 5 days ago by Robert McNamara 2 replies 147 views
Answered How long are the Cortex-M7 pipeline stages? Latest 8 days ago by Pacocha 18 replies 28376 views
Answered Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1? Latest 8 days ago by George_ 2 replies 2015 views
Answered Disable Cache L1 et L2 Armv8 Latest 12 days ago by 42Bastian Schick 7 replies 2516 views
Answered Is Advanced-SIMD supported in Cortex-R5F? Latest 15 days ago by Koppu 4 replies 4533 views
Answered Cortex-A7 pipeline is non-symmetric, what does this attribute mean? Latest 15 days ago by Jerome Decamps - 杜尚杰 10 replies 10055 views