Cortex-A8

The Cortex-A8 processor is a high-performance and low-power application processor that provides full virtual memory capabilities.

Information on Cortex-A8.

Getting Started

The Cortex-A8 was first introduced in 2005 and was the first processor to support the Armv7-A architecture. Since its introduction, the Cortex-A8 processor has been superseded by the Cortex-A15 and Cortex-A17 processors, but it represents a turning point upwards in the race for efficient high-performance 32-bit compute, and it is still widely deployed in many embedded applications.

Specifications

Architecture Armv7
Multicore Single core only
ISA Support
 
Memory Management Unit (MMU)
Armv7 Memory Management Unit (MMU)
Debug & Trace
CoreSight

Characteristics

The Cortex-A8 processor was the first to use the Armv7-A architecture. Armv7 incorporated three key elements: the Neon single instruction multiple data (SIMD) unit, Arm TrustZone security extensions, and the Thumb-2 instruction set for reduced code size via a mix of 16-bit and 32-bit extensions. The Cortex-A8 implements the extended ISA in the first ever fully superscalar design from Arm. It has a full dual-issue pipeline, meaning the Cortex-A8 can simultaneously issue any two instructions that occur sequentially in the instructions stream whose arguments do not have unresolved dependencies.

The processor has a number of features which make it ideal for use in high-performance end products. A symmetric, superscalar pipeline allows for full dual-issue capability and high-frequency configurations. There is an advanced branch prediction unit with over 95% accuracy, and an integrated L2 cache provides optimal performance in demanding systems. The Cortex-A8 supports Neon technology, allowing it to take advantage of accelerated multimedia and DSP processing.

The Arm Cortex-A8 processor has the ability to scale in speed from 600MHz to greater than 1GHz, meeting the requirements for power-optimized mobile devices needing operation in less than 300mW and performance-optimized consumer applications.


  • Manual containing technical information.
  • Cortex-A8 Technical Reference Manual

    For system designers and software engineers, the Cortex-A8 manual provides information on implementing and programming Cortex-A8 based devices.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the Guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode)
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A8 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A8 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A8 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-400 GPU

Mali Display Processors

Mali V500 Video Processor

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

Community Blogs

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Community Forums

Answered Binary Semaphore upset by FIQ
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Answered AXI4 Lite handshake
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Answered AARCH64 banked registers
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Answered Boot sequence and secure boot
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Discussion How AXI addressing works for fixed burst with unaligned address.
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0 votes 7894 views 7 replies Latest 20 days ago by Ajit Kakadiya Answer this
Answered Cortex-M0+ hangs on return
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0 votes 235 views 1 replies Latest 20 days ago by trf Answer this
Answered Binary Semaphore upset by FIQ Latest 4 days ago by 42Bastian Schick 20 replies 871 views
Answered AXI4 Lite handshake Latest 8 days ago by Christopher Tory 1 replies 378 views
Answered AARCH64 banked registers Latest 9 days ago by LdB 2 replies 373 views
Answered Boot sequence and secure boot Latest 15 days ago by LukaP 2 replies 1224 views
Discussion How AXI addressing works for fixed burst with unaligned address. Latest 20 days ago by Ajit Kakadiya 7 replies 7894 views
Answered Cortex-M0+ hangs on return Latest 20 days ago by trf 1 replies 235 views