Cortex-A9

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Cortex-A9 results

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Invalid Date NaN, NaN

regions configured in the TZC-400 and the source from where the AXI-low power signals are coming to TZC-400

Where does the 9 regions supported by the TZC-400 are present and the source from where the AXI-low power signals are connected to TZC-400

Invalid Date NaN, NaN

L2 Cache ECC Notification

I am trying to implement L2 ECC for A72 core and its notification. ... And L2 ECC system generates two error signals ... nEXTERRIRQ and nINTERRIRQ, ... I assume , nINTERRIRQ will be generated in case of double bit error.

Invalid Date NaN, NaN

Generic Interrupt Controller Usage

I enabled the Received Data Available interrupt on uart0 peripheral but I don't understand how to catch it and register the IRO to an ISR. ... The uart0_IRQ's GIC interrupt number is 140. ... Could you please help me about that?

Invalid Date NaN, NaN

Socrates for SSE-315 subsystem

#progblem ... I can't generate M85 subsystem. ... But I already download m85 ip package and r1p0 bounld successful. ... Can anyone help me to slove this problem ?

Invalid Date NaN, NaN

Exception return for Cortex-M7

I have a function that generates an UsageFault exception for test: ... UsageFault_Trigger_UnalignedAccess(void)

Invalid Date NaN, NaN

Why is the ACELS interface of the R82 prohibited from non-modifiable bursts?

Invalid Date NaN, NaN

Cortex-R52+ branch predictor

I'm facing a problem that the core runs on the NVM at first, then jump to the RAM code to do some operation for the same partition of the NVM. ... After the operation (code on the RAM) is completed, back the NVM for the following code execution.

Invalid Date NaN, NaN

Add custom CPU features

In virtualization scenarios, we can customize CPU features to implement some HV functions to improve VM performance or stability.

Invalid Date NaN, NaN

IMPRECISERR error when decrementing Stack Pointer

I am using a STM32F4 series board with Arm Cortex M4 processor to develop a simple scheduler for learning purposes. ... I have a code snippet where I first set up the stack start location for a task, and then initialize PSP (stack pointer) to its very first location, and then manually fill the stack with some values as follows:

Invalid Date NaN, NaN

GICv3 ICC_EOIR

The interrupt is handled by the following order: ... 1. save context ... 2. read ICC_IAR0, get INTID ... 3. jump to ISR of the associated INTID ... 4. write ICC_EOIR0 ... 5. restore context ... The IRQ is unmasked before writing ICC_EOIR0.

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regions configured in the TZC-400 and the source from where the AXI-low power signals are coming to TZC-400

Where does the 9 regions supported by the TZC-400 are present and the source from where the AXI-low power signals are connected to TZC-400