Arm Cortex-A Series Processors

The Arm Cortex-A series of applications processors provide a range of solutions for devices undertaking complex compute tasks, such as hosting a rich Operating System (OS) platform, and supporting multiple software applications.

Cortex-A Series Characteristics

All Armv7-A and Armv8-A based processor cores featured in the current Arm processor portfolio supports Arm's multicore technologies.

  • Up to eight-core implementations for all DynamIQ based processors
  • Up to quad-core implementation for all processors using Armv7-A and the original Armv8-A specification

Key features of the Cortex-A family of devices:

  • Scalable clusters supporting single and multi-core configurations
  • RISC cores with support for Armv7-A and Armv8-A architecture
  • Full backward compatibility with code from previous Arm processors
  • VFP and Neon units to execute floating-point and Advanced SIMD instruction sets
  • Optional Cryptographic accelerator engines supporting algorithms like AES, SHA1 and SHA2-256
  • Memory Management Support (MMU) supporting virtual address and physical address spaces with various page sizes
  • Hardware translation table walking for virtual to physical address translation
  • Big-endian and little-endian data access support
  • Unaligned access support for basic load/store instructions
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  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
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  • Learn the Armv8-A architecture

    Common to all Cortex-A series processors, these guides are useful for anyone developing assembly and C language applications for Armv8-A.

    Read the guides
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
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  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
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  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

    Learn more
  • Armv8-A Architecture

    Armv8-A architecture provides access to 64-bit wide integer registers and data operations, and the ability to use 64-bit sized pointers to memory. Armv8-A also includes the original Arm instruction set, now called A32.

    Learn more

Advanced features in Arm DynamIQ Cortex-A Processors

Cortex-A processors utilize multi-core technology to enables scalability from single up to four cores for traditional MPCore processors, and single up to eight cores for DynamIQ processors - this enables higher amounts of compute processing to take place within the CPU system. Multicore processing provides the ability for any of the four component processors, within a cluster, to shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is in use to meet the demand while still sharing the workload to keep power consumption as low as possible. Processors based on DynamIQ also improve on data security and privacy, advanced safety and RAS features, and integrated AI capabilities that enable DynamIQ-based systems to deliver a wide range of solutions. Advanced power management features integrated into the DynamIQ processors deliver higher amounts of power savings for energy-efficient designs.

Intelligent compute capabilities

Cortex-A CPUs that are designed based on DynamIQ technology can carry out advanced compute capabilities in Machine Learning and Artificial Intelligence.

Interfaces for closely coupled accelerators

DynamIQ technology provides the ability to closely couple Cortex-A CPUs with external accelerators and I/O-coherent IP, delivering up to 10x faster response times between CPU and specialized accelerator hardware on the SoC, compared to traditional clusters. This enables DynamIQ-based systems to carry out offload acceleration and I/O-coherent processing for applications such as cryptography acceleration and packet processing with higher performance and lower latency.

Built-in power-saving features

DynamIQ comes integrated with a host of new power management solutions. A more rapid and autonomous hardware-controlled power state transition mechanism reduces the latency between the power states supported by Arm Cortex-A CPUs, for example ON, OFF, and SLEEP. It also includes an autonomous CPU memory power solution, which intelligently adapts the amount of local memory available to the CPUs depending on the type of application running.

Additionally, DynamIQ technology enables finer-grained Dynamic Voltage and Frequency Scaling (DVFS) of individual and groups of CPUs in a DynamIQ cluster. This maximizes the achieved performance in devices that have a fixed thermal budget, while also providing more power savings from all applications of the technology.

DynamIQ big.LITTLE

Next-generation big.LITTLE Cortex-A CPU clusters can now be designed with a combination of high performance ‘big’ CPUs and high efficiency ‘LITTLE’ CPUs in one cluster, with a shared coherent memory. DynamIQ big.LITTLE delivers significant improvements in performance gained from a tighter, more coherent system. It also presents unprecedented flexibility and new choices in CPU topology, such as 1xbig + 7xLITTLE, to deliver purpose-built solutions.

Advanced RAS and safety features

DynamIQ processors support higher levels of safety requirements such as ASIL D and SIL-3. All DynamIQ-based IP are taken through a rigorous design flow to avoid systematic faults.  Additionally, safety-related application performance is improved with shorter latency in decision making and actuation across AI scenarios such as Advanced Driver Assistance Systems (ADAS) for autonomous vehicles. DynamIQ based systems also come integrated with advanced features that improve Reliability, Availability and Serviceability (RAS) for applications such as industrial and infrastructure.


Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A