Cortex-M0

The Arm Cortex-M0 processor is the smallest Arm processor available. 

Information on Cortex-M0.

Getting Started

The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices.

The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices. Arm DesignStart provides free access to design and license the Cortex-M0, and free forum support to accelerate custom SoC development. It is the fastest, simplest, no-risk route to custom silicon success.

Download this whitepaper for tips and tools to creating an SoC proof-of-concept, free and fast!


Specifications

ISA Support Thumb/Thumb-2 subset
Pipeline

3-stages

Bit Manipulation
Bit banding region can be implemented with Cortex-M System Design Kit
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Enhanced Instructions
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Compare all Cortex-M processors

Cortex-M0 Characteristics

Performance Efficiency 2.33 CoreMarks/MHz* and 0.89/1.02/1.27 DMIPS/MHz.

Arm Cortex-M0 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C) 
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power

66μW/MHz 

12.5μW/MHz 

5.3μW/MHz 

Floor planned Area

0.11 mm2

0.03 mm2

0.008 mm2

* See: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1509&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi- le”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

*** Configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug


  • Manual containing technical information.
  • Cortex-M0 Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0.

    Read here
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • A system design kit for apps.
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box.

    Learn more

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz**
2.33 2.46  1.85
2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
                                                                                                                                                                                                                                                                                                             

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? 0 votes 10 views 0 replies Started 6 hours ago by jpthibault Answer this
Not answered why does LDR takes two cycle to be executed 0 votes 21 views 0 replies Started 10 hours ago by Haohao Answer this
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state?
  • Armv8-A
  • AArch32
0 votes 65 views 1 replies Latest 20 hours ago by 42Bastian Schick Answer this
Suggested answer How to Change the Non Secure VTOR (Cortex-M33)
  • TrustZone for Armv8-M
  • Trusted Execution Environment (TEE)
  • TrustZone
  • Cortex-M33
  • Armv8-M
0 votes 92 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer How to import C variable in an assembly code in a .s file
  • Cortex-M
  • cortex-m0+
  • Arm Assembly Language (ASM)
0 votes 69 views 1 replies Latest yesterday by Georgia James Answer this
Answered Watchdog timer not entering ISR
  • Cortex-A9
  • Interrupt Controller Devices
  • Cortex-A
  • Interrupt
0 votes 109 views 2 replies Latest yesterday by sherry Answer this
Not answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? Started 6 hours ago by jpthibault 0 replies 10 views
Not answered why does LDR takes two cycle to be executed Started 10 hours ago by Haohao 0 replies 21 views
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state? Latest 20 hours ago by 42Bastian Schick 1 replies 65 views
Suggested answer How to Change the Non Secure VTOR (Cortex-M33) Latest yesterday by 42Bastian Schick 1 replies 92 views
Suggested answer How to import C variable in an assembly code in a .s file Latest yesterday by Georgia James 1 replies 69 views
Answered Watchdog timer not entering ISR Latest yesterday by sherry 2 replies 109 views