The Arm Cortex-M0 processor is one of the smallest Arm processors available.

The Cortex-M0 has an exceptionally small silicon area, low power and minimal code footprint, enabling developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The ultra-low gate count of the processor enables its deployment in analog and mixed signal devices.

Information on Cortex-M0.

Arm Cortex-M0 processor

Architecture Armv6-M
Bus Interface
AHB-Lite, Von Neumann bus architecture
ISA Support Thumb/Thumb-2 subset
Pipeline 3-stages
Bit Manipulation
Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller
Enhanced Instructions 
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Optional JTAG and Serial Wire Debug ports. Up to 4 Breakpoints and 2 Watchpoints
Reference package or system example

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Cortex-M0 Characteristics

Performance Efficiency 2.33 CoreMark/MHz* and 0.96/1.19/1.91 DMIPS/MHz.**

Arm Cortex-M0 implementation data***
(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
Dynamic power 66 μW/MHz  12.5 μW/MHz 5.3 μW/MHz 
Floor planned area 0.11 mm2 0.03 mm2 0.008 mm2

* See: EEMBC Benchmark Score Viewer

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone. Arm Compiler 6.17 

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug