Cortex-M0

The Arm Cortex-M0 processor is one of the smallest Arm processors available. 

Information on Cortex-M0.

Getting Started

The Cortex-M0 has an exceptionally small silicon area, low power and minimal code footprint, enabling developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The ultra-low gate count of the processor enables its deployment in analog and mixed signal devices.


Specifications

Architecture Armv6-M
Bus Interface
AHB-Lite, Von Neumann bus architecture
ISA Support Thumb/Thumb-2 subset
Pipeline 3-stages
Bit Manipulation
Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller
Optional
Enhanced Instructions 
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 4 Breakpoints and 2 Watchpoints

Compare all Cortex-M processors

Start designing with Cortex-M0

Cortex-M0 is available to access for $0 upfront for prototyping and commercializing a custom SoC with Arm DesignStart. Alternatively, if you would like to design with Cortex-M0 and additional Arm IP, Arm Flexible Access delivers unlimited design access to a wide range of IP products, support, tools and training – with payment due only at the point of manufacture.

Cortex-M0 Characteristics

Performance Efficiency 2.33 CoreMark/MHz* and 0.89/1.02/1.27 DMIPS/MHz.**

Arm Cortex-M0 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C) 
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power

66 μW/MHz 

12.5 μW/MHz 

5.3 μW/MHz 

Floor Planned Area

0.11 mm2

0.03 mm2

0.008 mm2

* See: EEMBC Benchmark Score Viewer

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug



Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M55
Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv8.1-M Mainline
Helium
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5   1.6 2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02  4.2 5.01
Pipeline Stages
 4
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) (2 x)
Yes (option) 
Maximum MPU Regions  16  16  16  16
16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
ETMv4 (option)
Digital Signal Processing (DSP) extension
No  No  No  No  No Yes  Yes (option) Yes (option)  Yes (option)
Yes 
Floating Point Hardware  No No  No  No  No Yes (scalar SP) Yes (scalar SP) Yes (scalar SP) Yes (scalar HP +
SP + DP) (vector
HP + SP)
Yes (scalar SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes (2 x)
Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option)
Yes (option 4-64kB 
 I-cache I-cache and D-cache
I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM)
Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  Yes (option)
No 
Coprocessor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  Yes (option)
No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI5 (main bus), AHB
(peripheral bus,
TCM slave port and debug)
AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 480
240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes
Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  No
Yes 
Arm Custom Instructions
No
No
No
No
No
No
Yes
No
Yes (available in 2021)
No

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision

Related IP

The Cortex-M0 processor can be incorporated into a SoC using a broad range of Arm technology including, System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS 

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Answered Non-secure configuration of UART1 on Arm Musca-A1
  • Musca-A
  • TrustZone for Armv8-M
0 votes 198 views 4 replies Latest 6 hours ago by Daniel Oliveira Answer this
Not answered Timer interrupts synchronization in Cortex M4
  • Cortex-M4
  • Interrupt
0 votes 27 views 0 replies Started 6 hours ago by satheesh21 Answer this
Not answered Arm64 Long Format Translation Table Walk
  • Armv8-A
  • Memory Management Unit (MMU)
0 votes 84 views 0 replies Started 10 hours ago by angeld Answer this
Suggested answer How long does it take for Cortex A53 to exit low power state? 0 votes 326 views 2 replies Latest 11 hours ago by Andy Neil Answer this
Suggested answer Optimization of Neon Intrinsics on ARM cortexa53
  • Cortex-A53
  • AArch64
  • Optimization Solution
  • GCC
  • NEON
  • Arm Assembly Language (ASM)
0 votes 699 views 12 replies Latest 14 hours ago by 42Bastian Schick Answer this
Answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)
  • CoreSight Architecture
  • Cortex-M
  • Debugging
  • CoreSight
  • Cortex-M4
0 votes 309 views 1 replies Latest 16 hours ago by 42Bastian Schick Answer this
Answered Non-secure configuration of UART1 on Arm Musca-A1 Latest 6 hours ago by Daniel Oliveira 4 replies 198 views
Not answered Timer interrupts synchronization in Cortex M4 Started 6 hours ago by satheesh21 0 replies 27 views
Not answered Arm64 Long Format Translation Table Walk Started 10 hours ago by angeld 0 replies 84 views
Suggested answer How long does it take for Cortex A53 to exit low power state? Latest 11 hours ago by Andy Neil 2 replies 326 views
Suggested answer Optimization of Neon Intrinsics on ARM cortexa53 Latest 14 hours ago by 42Bastian Schick 12 replies 699 views
Answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR) Latest 16 hours ago by 42Bastian Schick 1 replies 309 views