Cortex-M0

The Arm Cortex-M0 processor is one of the smallest Arm processors available. 

Information on Cortex-M0.

Getting Started

The Cortex-M0 has an exceptionally small silicon area, low power and minimal code footprint, enabling developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The ultra-low gate count of the processor enables its deployment in analog and mixed signal devices.


Specifications

Architecture Armv6-M
Bus Interface
AHB-Lite, Von Neumann bus architecture
ISA Support Thumb/Thumb-2 subset
Pipeline 3-stages
Bit Manipulation
Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller
Optional
Enhanced Instructions 
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 4 Breakpoints and 2 Watchpoints

Compare all Cortex-M processors

Start designing with Cortex-M0

Cortex-M0 is available to access for $0 upfront for prototyping and commercializing a custom SoC with Arm DesignStart. Alternatively, if you would like to design with Cortex-M0 and additional Arm IP, Arm Flexible Access delivers unlimited design access to a wide range of IP products, support, tools and training – with payment due only at the point of manufacture.

Cortex-M0 Characteristics

Performance Efficiency 2.33 CoreMark/MHz* and 0.89/1.02/1.27 DMIPS/MHz.**

Arm Cortex-M0 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C) 
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power

66 μW/MHz 

12.5 μW/MHz 

5.3 μW/MHz 

Floor Planned Area

0.11 mm2

0.03 mm2

0.008 mm2

* See: EEMBC Benchmark Score Viewer

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug



Related IP

The Cortex-M0 processor can be incorporated into a SoC using a broad range of Arm technology including, System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

CoreLink AHB Cache

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS 

Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M55
Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv8.1-M Mainline
Helium
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5   1.6 2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02  4.2 5.01
Pipeline Stages
 4
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) (2 x)
Yes (option) 
Maximum MPU Regions  16  16  16  16
16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
ETMv4 (option)
Digital Signal Processing (DSP) extension
No  No  No  No  No Yes  Yes (option) Yes (option)  Yes (option)
Yes 
Floating Point Hardware  No No  No  No  No Yes (scalar SP) Yes (scalar SP) Yes (scalar SP) Yes (scalar HP +
SP + DP) (vector
HP + SP)
Yes (scalar SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes (2 x)
Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option)
Yes (option 4-64kB 
 I-cache I-cache and D-cache
I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM)
Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  Yes (option)
No 
Coprocessor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  Yes (option)
No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI5 (main bus), AHB
(peripheral bus,
TCM slave port and debug)
AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 480
240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes
Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  No
Yes 
Arm Custom Instructions
No
No
No
No
No
No
Yes
No
Yes (available in 2021)
No
Common Criteria certification No No  No  No  No  No  Yes  Yes  No No 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision

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0 votes 87 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer Tasks can't switch to others, always run at OSStartHang. but whitout boot code ,the app can run ok. the core of the chip is cortex-M0 0 votes 2856 views 7 replies Latest 2 days ago by John_shi Answer this
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0 votes 1313 views 5 replies Latest 3 days ago by vstehle Answer this
Suggested answer Which bit fields are for Cortex-M4F SCB_ICSR.VECTORPENDING Latest yesterday by 42Bastian Schick 1 replies 87 views
Suggested answer Tasks can't switch to others, always run at OSStartHang. but whitout boot code ,the app can run ok. the core of the chip is cortex-M0 Latest 2 days ago by John_shi 7 replies 2856 views
Not answered SVCall returning to 0xdeadbeee Started 2 days ago by DanS 0 replies 164 views
Not answered How to test L1/L2 cache? Started 3 days ago by Zhiping Jiang 0 replies 171 views
Not answered V2C-DAPLINK-035A shield schematic Started 3 days ago by Brix 0 replies 52 views
Answered Speculative execution/loads on Cortex-A5 Latest 3 days ago by vstehle 5 replies 1313 views