Cortex-M0+

The Arm Cortex-M0+ processor is the most energy-efficient Arm processor available for constrained embedded applications.

Block Diagram on Cortex-M0+.

Getting Started

The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance.

The exceptionally small silicon area, low power and minimal code footprint of Cortex-M0+ enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.


Specifications

Architecture Armv6-M
Bus Interface
AHB-Lite, Von Neumann bus architecture with optional single-cycle I/O interface
ISA Support Thumb/Thumb-2 subset
Pipeline 2-stage
Memory Protection Optional 8 region MPU with sub regions and background region
Bit Manipulation
Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller
Optional
Enhanced Instructions
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG or Serial Wire Debug ports. Up to 4 Breakpoints and 2 Watchpoints
Trace
Optional Micro Trace Buffer

Compare all Cortex-M processors

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Characteristics

Performance Efficiency 2.46 CoreMark/MHz* and 0.95/1.11/1.36 DMIPS/MHz**.

Arm Cortex-M0+ Implementation Data***

180ULL 
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP 
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floor Planned Area 0.098 mm2 0.028 mm2 0.0066 mm2

* See http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1526&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.


  • Manual containing technical information.
  • Cortex-M0+ Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0+.

    Read here
  • A program that is running on a desktop.
  • Cortex-M0+ Devices Generic User Guide

    For application and system level software developers, the Devices Generic User Guide provides programming information for the Cortex-M0+ processor.

    Read here
  • Papers filed, in a formal order.
  • Armv6-M Architecture Reference Manual

    This manual describes the instruction set, memory model, and programmers' model for Armv6-M compliant processors. 


    Read here
  • a ulink, a board, a desktop.
  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • Systems supporting the main system.
  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here
  • Line drawing of letter, email etc.
  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors. 

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M0+ processor can be incorporated into a SoC using a broad range of Arm technology including System IP, and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK software development tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries 

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

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0 votes 52 views 1 replies Latest yesterday by Andy Neil Answer this
Not answered Is return stack buffer implemented in Zync 7000 Soc Started 11 hours ago by alireza11048 0 replies 13 views
Suggested answer ARMv8 memory ordering Latest 14 hours ago by a.surati 7 replies 1091 views
Not answered gicv3 aarch32 icc_hsre Started yesterday by PJ Nee 0 replies 33 views
Suggested answer NVIC_EnableIRQ : enables only one interrupt at a time? Latest yesterday by Andy Neil 3 replies 74 views
Suggested answer Is there a built-in ARM assembly instruction for the following problem? Latest yesterday by Andy Neil 1 replies 59 views
Suggested answer Is it possible to get keyboard input into an ARM Assembly program? Latest yesterday by Andy Neil 1 replies 52 views