Cortex-M0+

The Arm Cortex-M0+ processor is the most energy-efficient Arm processor available.

Block Diagram on Cortex-M0+.

Getting Started

The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.

Specifications

ISA Support Thumb/Thumb-2 subset.
Pipeline 2-stage.
Memory Protection
Optional 8 region MPU with sub regions and background region.
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts.
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit.
Bit Manipulation
Bit banding region can be implemented with Cortex-M System Design Kit.
Enhanced Instructions
Hardware single-cycle (32x32) multiply option.
Debug
Optional JTAG or Serial Wire Debug ports Up to 4 Breakpoints and 2 Watchpoints.
Trace
Optional Micro Trace Buffer.

Compare all Cortex-M processors

Characteristics

Performance Efficiency 2.46 CoreMarks/MHz* and 0.95/1.11/1.35 DMIPS/MHz**.

Arm Cortex-M0+ Implementation Data***
180ULL 
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP 
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floorplan Area 0.098 mm2 0.028 mm2 0.0066 mm2

http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1526&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

*** Base usable configuration includes 1 IRQ + NMI, excludes debug.


Related IP

The Cortex-M0+ processor can be incorporated into a SoC using a broad range of Arm technology including System IP, and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
Tools
Software

Cortex-M System Design Kit

Socrates System IP Tooling

AMBA System Controllers

DS-5 Development Studio

Arm Keil MDK software development tool

Cortex-M Prototyping System

Cortex Microcontroller Software Interface Standard

Arm Mbed Pelion Device Platform

Software Test Libraries 


  • Manual containing technical information.
  • Cortex-M0+ Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0+.

    Read here
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz**
2.33 2.46  1.85
2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
                                                                                                                                                                                                                                                                                                             

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? 0 votes 11 views 0 replies Started 7 hours ago by jpthibault Answer this
Not answered why does LDR takes two cycle to be executed 0 votes 22 views 0 replies Started 11 hours ago by Haohao Answer this
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state?
  • Armv8-A
  • AArch32
0 votes 66 views 1 replies Latest 21 hours ago by 42Bastian Schick Answer this
Suggested answer How to Change the Non Secure VTOR (Cortex-M33)
  • TrustZone for Armv8-M
  • Trusted Execution Environment (TEE)
  • TrustZone
  • Cortex-M33
  • Armv8-M
0 votes 92 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer How to import C variable in an assembly code in a .s file
  • Cortex-M
  • cortex-m0+
  • Arm Assembly Language (ASM)
0 votes 72 views 1 replies Latest yesterday by Georgia James Answer this
Answered Watchdog timer not entering ISR
  • Cortex-A9
  • Interrupt Controller Devices
  • Cortex-A
  • Interrupt
0 votes 109 views 2 replies Latest yesterday by sherry Answer this
Not answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? Started 7 hours ago by jpthibault 0 replies 11 views
Not answered why does LDR takes two cycle to be executed Started 11 hours ago by Haohao 0 replies 22 views
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state? Latest 21 hours ago by 42Bastian Schick 1 replies 66 views
Suggested answer How to Change the Non Secure VTOR (Cortex-M33) Latest yesterday by 42Bastian Schick 1 replies 92 views
Suggested answer How to import C variable in an assembly code in a .s file Latest yesterday by Georgia James 1 replies 72 views
Answered Watchdog timer not entering ISR Latest yesterday by sherry 2 replies 109 views