The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.
|ISA Support||Thumb/Thumb-2 subset.|
||Optional 8 region MPU with sub regions and background region.|
|Interrupts||Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts.|
||Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit.
||Bit banding region can be implemented with Cortex-M System Design Kit.|
||Hardware single-cycle (32x32) multiply option.|
||Optional JTAG or Serial Wire Debug ports Up to 4 Breakpoints and 2 Watchpoints.|
||Optional Micro Trace Buffer.|
|Dual Core Lock-Step Support
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.
Performance Efficiency 2.46 CoreMarks/MHz* and 0.95/1.11/1.35 DMIPS/MHz**.
|Arm Cortex-M0+ Implementation Data***|
(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
|Dynamic Power||47.4 µW/MHz||9.37 µW/MHz||3.8 µW/MHz|
|Floorplan Area||0.098 mm2||0.028 mm2||0.0066 mm2|
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.
*** Base usable configuration includes 1 IRQ + NMI, excludes debug.
The Cortex-M0+ processor can be incorporated into a SoC using a broad range of Arm technology including System IP, and Physical IP. It is fully supported by Arm development tools. Related IP includes:
Cortex-M0+ Technical Reference Manual
In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0+.Read here
White Paper: Cortex-M for beginners
This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.Read here
Embedded Development Tools for Cortex-M Series
Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.Learn more
Cortex-M Comparison Table
|Instruction set architecture||Armv6-M||Armv6-M
|Thumb, Thumb-2||Thumb, Thumb-2
|Memory Protection Unit (MPU)||No||Yes (option)||No||Yes (option)
|Yes (option)||Yes (option)||Yes (option)
|Maximum MPU regions||0||8||0||16||8||8||16||16||16|
|Trace (ETM or MTB)||No||MTB (option)||No||MTB (option) or
|ETMv3 (option)||ETMv3 (option)||MTB (option) and/or
MTB (option) and/or
|DSP||No||No||No||No||No||Yes||Yes (option)||Yes (option)||Yes|
|Floating point hardware||No||No||No||No||No||Yes (option SP)||Yes (option SP)||Yes (option SP)||Yes
(option SP + DP)
||Yes (option)||Yes (option)||Yes (option)||Yes (2 x)||Yes||Yes||Yes (2 x)||Yes (2 x)||Yes|
|Built-in Caches||No||No||No||No||No||No||No||Yes (option 2- 16kB||Yes (option 4-64kB|
|I-cache||I-cache, D -cache)|
|Tightly Coupled Memory||No||No||Yes||No||No||No||No||No||Yes
|TrustZone for Armv8-M
||No||No||No||Yes (option)||No||No||Yes (option)||Yes (option)||No|
|Co-processor interface||No||No||No||No||No||No||Yes (option)||Yes (option)||No|
||AHB Lite||AHB Lite, Fast I/O||AHB Lite||AHB5, Fast I/O||AHB Lite, APB||AHB Lite, APB||AHB5||AHB5||AXI4, AHB Lite, APB, TCM
|Wake-up interrupt controller support
|Integrated interrupt controller
|Maximum # external interrupts
|Single cycle multiply
||Yes (option)||Yes (option)||No||Yes||Yes||Yes||Yes||Yes||Yes|
|Dual Core Lock-Step Support
*See individual Cortex-M product pages for further information.
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
|Suggested answer||Monitor Mode Debug||0 votes||495 views||6 replies||Latest 5 hours ago by Andy Neil||Answer this|
|Not answered||Can i change SP at run time in CM33?||0 votes||23 views||0 replies||Started 5 hours ago by Deepak||Answer this|
|Not answered||Audio mixing efficiently and hard realtime requirment||0 votes||49 views||0 replies||Started 15 hours ago by Manojkumar Subramaniam||Answer this|
|Not answered||Are there any Cortex-M controller with h.264 encoder?||0 votes||59 views||0 replies||Started yesterday by Vick||Answer this|
|Answered||32-bit encoding hex values for Arm instructions||0 votes||263 views||3 replies||Latest yesterday by BQL||Answer this|
|Suggested answer||Memory Protection Unit - Complexity in usage||0 votes||434 views||5 replies||Latest 2 days ago by 42Bastian Schick||Answer this|
|Suggested answer||Monitor Mode Debug Latest 5 hours ago by Andy Neil||6 replies 495 views|
|Not answered||Can i change SP at run time in CM33? Started 5 hours ago by Deepak||0 replies 23 views|
|Not answered||Audio mixing efficiently and hard realtime requirment Started 15 hours ago by Manojkumar Subramaniam||0 replies 49 views|
|Not answered||Are there any Cortex-M controller with h.264 encoder? Started yesterday by Vick||0 replies 59 views|
|Answered||32-bit encoding hex values for Arm instructions Latest yesterday by BQL||3 replies 263 views|
|Suggested answer||Memory Protection Unit - Complexity in usage Latest 2 days ago by 42Bastian Schick||5 replies 434 views|