Cortex-M0+

The Arm Cortex-M0+ processor is the most energy-efficient Arm processor available for constrained embedded applications.

Block Diagram on Cortex-M0+.

Getting Started

The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance.

The exceptionally small silicon area, low power and minimal code footprint of Cortex-M0+ enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.


Specifications

Architecture Armv6-M
Bus Interface
AMBA AHB-Lite, Von Neumann bus architecture with optional single-cycle I/O interface
ISA Support Thumb/Thumb-2 subset
Pipeline 2-stage
Memory Protection Optional 8 region MPU with sub regions and background region
Bit Manipulation
Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller
Optional
Enhanced Instructions
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG or Serial Wire Debug ports. Up to 4 Breakpoints and 2 Watchpoints
Trace
Optional Micro Trace Buffer

Compare all Cortex-M processors

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Characteristics

Performance Efficiency 2.46 CoreMark/MHz* and 0.95/1.11/1.36 DMIPS/MHz**.

Arm Cortex-M0+ Implementation Data***

180ULL 
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP 
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floor Planned Area 0.098 mm2 0.028 mm2 0.0066 mm2

* See http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1526&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.



Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M0+ processor can be incorporated into a SoC using a broad range of Arm technology including System IP, and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK software development tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries 

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered BURST option in AHB-to-AHB sync-up bridge 0 votes 271 views 0 replies Started 13 hours ago by misimovi Answer this
Suggested answer How to access memory more than 4GB by using 32bit ISA?
  • Memory Access Instructions
0 votes 624 views 5 replies Latest 16 hours ago by Martin Weidmann Answer this
Suggested answer Saving processor state for power-down and resume
  • Thumb
  • Cortex-M4
0 votes 124 views 1 replies Latest 20 hours ago by 42Bastian Schick Answer this
Suggested answer adc read
  • Cortex-M0
0 votes 114 views 1 replies Latest 21 hours ago by 42Bastian Schick Answer this
Not answered How to write values ​​from secure code to non-secure memory.
  • TrustZone for Armv8-M
0 votes 138 views 0 replies Started yesterday by Lars Answer this
Not answered Cache Coherence Support in CHI Specification 0 votes 370 views 0 replies Started 2 days ago by JO16 Answer this
Not answered BURST option in AHB-to-AHB sync-up bridge Started 13 hours ago by misimovi 0 replies 271 views
Suggested answer How to access memory more than 4GB by using 32bit ISA? Latest 16 hours ago by Martin Weidmann 5 replies 624 views
Suggested answer Saving processor state for power-down and resume Latest 20 hours ago by 42Bastian Schick 1 replies 124 views
Suggested answer adc read Latest 21 hours ago by 42Bastian Schick 1 replies 114 views
Not answered How to write values ​​from secure code to non-secure memory. Started yesterday by Lars 0 replies 138 views
Not answered Cache Coherence Support in CHI Specification Started 2 days ago by JO16 0 replies 370 views