The Arm Cortex-M0+ processor is the most energy-efficient Arm processor available for constrained embedded applications.

The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance.

The exceptionally small silicon area, low power and minimal code footprint of Cortex-M0+ enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.

Block Diagram on Cortex-M0+.

Arm Cortex-M0+ processor

Architecture Armv6-M
Bus Interface
AMBA AHB-Lite, Von Neumann bus architecture with optional single-cycle I/O interface
ISA Support Thumb/Thumb-2 subset
Pipeline 2-stage
Memory Protection Optional 8 region MPU with sub regions and background region
Bit Manipulation
Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller
Enhanced Instructions
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Optional JTAG or Serial Wire Debug ports. Up to 4 Breakpoints and 2 Watchpoints
Optional Micro Trace Buffer
Reference package or system example

Compare the specifications of Cortex-M processors:
Download comparison table

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.

Learn more


Performance Efficiency 2.46 CoreMark/MHz* and 0.99/1.30/2.58 DMIPS/MHz**.

Arm Cortex-M0+ Implementation Data***

(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floor Planned Area 0.098 mm2 0.028 mm2 0.0066 mm2

* See: EEMBC Benchmark Score Viewer

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone. Arm Compiler 6.17.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.