Cortex-M1

The first Arm processor designed specifically for implementation in FPGAs. 

Getting Started

The Cortex-M1 processor targets FPGA devices and includes support for leading FPGA synthesis tools allowing the designer to choose the optimal implementation for each project. The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor.

Key features

  • Three-stage, 32-bit RISC processor
  • Thumb-2 instruction set
  • Integrated nested vectored interrupt controller
  • Fast or small multiplier configuration options

DesignStart FPGA

Get instant access to Cortex-M1 on Xilinx FPGA.

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Specifications

Architecture Armv6-M
ISA Thumb and Thumb-2 (except CBZ, CBNZ, IT, BL, DMB, DSB, ISB, MRS, MSR)
Pipeline Three-stage
SysTick Timer Optional
Bit Manipulation Optional bit-banding
Interrupts 1 – 32 interrupts (configurable)
Interrupt Priority Levels 4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories 0K - 1024K (configurable)
Debug Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)

Compare all Cortex-M processors

  • Manual containing technical information.

  • Cortex-M1 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M1 processor.

    Read here
  • Manual containing technical information.

  • Cortex-M1 FPGA Development Kit Cortex-M1 User Guide

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in their own SoC design using an Altera FPGA and Altera System-On-a-Programmable-Chip (SOPC) Builder. 

    Read here
  • a ulink, a board, a desktop.

  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • Manual containing technical information.

  • Cortex-M Resources

    Further resources for Cortex-M developers. 

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz**
 2.33 2.46  1.85
 2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
 3  2  3  2  3  3  3  3  6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) 
Maximum MPU regions  0  8  0  16  8  8  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
 32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
                                                                                                                                                                                                                                                                                                             

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M1 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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Community Forums

Suggested answer Axi4 Write Transaction 0 votes 32 views 1 replies Latest 10 hours ago by vstehle Answer this
Not answered The Peripherals memory map of FVP_BaseR_Cortex-R52x1
  • cortex-r52
  • Fixed Virtual Platforms (FVPs)
  • PrimeCell UART (PL011)
 0 votes 48 views 0 replies Started yesterday by Jex1x Answer this
Suggested answer Basic difference between "Generic User Guide" and "Technical Reference Manual" 0 votes 110 views 1 replies Latest 2 days ago by 42Bastian Schick Answer this
Suggested answer VMSAv8-64 and spinlock 0 votes 825 views 3 replies Latest 4 days ago by Ciro Donnarumma Answer this
Not answered Event Recorder with STM32F0
  • Cortex-M0
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  • event
 0 votes 74 views 0 replies Started 5 days ago by NSharp Answer this
Answered A question aboout Monitor Vector Base Address Register(MVBAR)
  • Cortex-A9
  • TrustZone
 0 votes 383 views 6 replies Latest 5 days ago by scribnote5 Answer this
Suggested answer Axi4 Write Transaction Latest 10 hours ago by vstehle 1 replies 32 views
Not answered The Peripherals memory map of FVP_BaseR_Cortex-R52x1 Started yesterday by Jex1x 0 replies 48 views
Suggested answer Basic difference between "Generic User Guide" and "Technical Reference Manual" Latest 2 days ago by 42Bastian Schick 1 replies 110 views
Suggested answer VMSAv8-64 and spinlock Latest 4 days ago by Ciro Donnarumma 3 replies 825 views
Not answered Event Recorder with STM32F0 Started 5 days ago by NSharp 0 replies 74 views
Answered A question aboout Monitor Vector Base Address Register(MVBAR) Latest 5 days ago by scribnote5 6 replies 383 views