Cortex-M1

The first Arm processor designed specifically for implementation in FPGAs. 

Getting Started

The Cortex-M1 processor targets FPGA devices and includes support for leading FPGA synthesis tools, allowing the designer to choose the optimal implementation for each project.

The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor.

Arm DesignStart FPGA provides instant and free access to Cortex-M1 soft CPU IP for use on FPGA designs for prototypes and commercial deployments.

Learn more about DesignStart.

Arm Cortex-M1 chip diagram

Specifications

Architecture Armv6-M
Bus Interface AMBA  AHB-Lite, Von Neumann Bus Architecture with optional Tightly Coupled Memory interfaces (I-TCM and D-TCM)
ISA Support Thumb/Thumb-2 subset
Pipeline Three-stage
SysTick Timer Optional
Multiplier Options of fast or area optimized 32-x32 multiplier
Bit Manipulation Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable interrupt (NMI) +1 to 32 interrupts (configurable)
Wakeup Interrupt Controller None
Interrupt Priority Levels 4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories 0K - 1024K (configurable)
Debug Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)

Compare all Cortex-M processors

Characteristics

Performance Efficiency: 1.85 CoreMark/MHz* and 0.8 DMIPS/MHz

  • Manual containing technical information.

  • Cortex-M1 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M1 processor.

    Read here
  • Papers filed, in a formal order.

  • Armv6-M Architecture Reference Manual

    This manual describes the instruction set, memory model, and programmers' model for Armv6-M compliant processors. 


    Read here
  • Tools and durable equipment.

  • Cortex-M1 FPGA Development Kit - GOWIN

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in a GOWIN-based FPGA design.

    Read here
  • a ulink, a board, a desktop.

  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • Tools and durable equipment.

  • Cortex-M1 FPGA Development Kit - Xilinx

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in an Xilinx-based FPGA design

    Read here
  • Line drawing of letter, email etc.

  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors.

    Read here
Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
 2.33 2.46  1.85
 2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
 3  2  3  2  3  3  3  3  6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) 
Maximum MPU Regions  0  8  0  16  8  8  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
 32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
 No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M1 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

Not answered BURST option in AHB-to-AHB sync-up bridge 0 votes 271 views 0 replies Started 14 hours ago by misimovi Answer this
Suggested answer How to access memory more than 4GB by using 32bit ISA?
  • Memory Access Instructions
 0 votes 627 views 5 replies Latest 17 hours ago by Martin Weidmann Answer this
Suggested answer Saving processor state for power-down and resume
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  • Cortex-M4
 0 votes 124 views 1 replies Latest 21 hours ago by 42Bastian Schick Answer this
Suggested answer adc read
  • Cortex-M0
 0 votes 114 views 1 replies Latest 22 hours ago by 42Bastian Schick Answer this
Not answered How to write values ​​from secure code to non-secure memory.
  • TrustZone for Armv8-M
 0 votes 138 views 0 replies Started yesterday by Lars Answer this
Not answered Cache Coherence Support in CHI Specification 0 votes 370 views 0 replies Started 2 days ago by JO16 Answer this
Not answered BURST option in AHB-to-AHB sync-up bridge Started 14 hours ago by misimovi 0 replies 271 views
Suggested answer How to access memory more than 4GB by using 32bit ISA? Latest 17 hours ago by Martin Weidmann 5 replies 627 views
Suggested answer Saving processor state for power-down and resume Latest 21 hours ago by 42Bastian Schick 1 replies 124 views
Suggested answer adc read Latest 22 hours ago by 42Bastian Schick 1 replies 114 views
Not answered How to write values ​​from secure code to non-secure memory. Started yesterday by Lars 0 replies 138 views
Not answered Cache Coherence Support in CHI Specification Started 2 days ago by JO16 0 replies 370 views