Cortex-M1

The first Arm processor designed specifically for implementation in FPGAs. 

Getting Started

The Cortex-M1 processor targets FPGA devices and includes support for leading FPGA synthesis tools allowing the designer to choose the optimal implementation for each project. The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor.

Key features

  • Three-stage, 32-bit RISC processor
  • Thumb-2 instruction set
  • Integrated nested vectored interrupt controller
  • Fast or small multiplier configuration options

DesignStart FPGA

Get instant and free access to Cortex-M1 soft IP for evaluation, research and commercial production with Arm's FPGA partners.

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Specifications

Architecture Armv6-M
ISA Thumb and Thumb-2 (except CBZ, CBNZ, IT, BL, DMB, DSB, ISB, MRS, MSR)
Pipeline Three-stage
SysTick Timer Optional
Bit Manipulation Optional bit-banding
Interrupts 1 – 32 interrupts (configurable)
Interrupt Priority Levels 4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories 0K - 1024K (configurable)
Debug Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)

Compare all Cortex-M processors

  • Manual containing technical information.

  • Cortex-M1 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M1 processor.

    Read here
  • Manual containing technical information.

  • Cortex-M1 FPGA Development Kit Cortex-M1 User Guide

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in their own SoC design using an Altera FPGA and Altera System-On-a-Programmable-Chip (SOPC) Builder. 

    Read here
  • a ulink, a board, a desktop.

  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • Manual containing technical information.

  • Cortex-M Resources

    Further resources for Cortex-M developers. 

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz**
 2.33 2.46  1.85
 2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
 3  2  3  2  3  3  3  3  6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) 
Maximum MPU regions  0  8  0  16  8  8  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
 32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
                                                                                                                                                                                                                                                                                                             

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M1 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

Not answered Trigger a Software Interrupt 0 votes 14 views 0 replies Started 9 hours ago by Aquox Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
 0 votes 110 views 3 replies Latest 13 hours ago by 42Bastian Schick Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 45 views 0 replies Started 2 days ago by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
 0 votes 877 views 20 replies Latest 5 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 65 views 0 replies Started 5 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 69 views 0 replies Started 5 days ago by BAB Answer this
Not answered Trigger a Software Interrupt Started 9 hours ago by Aquox 0 replies 14 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 13 hours ago by 42Bastian Schick 3 replies 110 views
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 2 days ago by jing 0 replies 45 views
Answered Binary Semaphore upset by FIQ Latest 5 days ago by 42Bastian Schick 20 replies 877 views
Not answered Identifying Generic IP Components on an Access Port Started 5 days ago by Torsten Robitzki 0 replies 65 views
Not answered Issue with WatchDog reset De-asserting Started 5 days ago by BAB 0 replies 69 views