Specifications
The Cortex-M23 processor is a very compact, two-stage pipelined processor that supports the Armv8-M baseline instruction set. The Cortex-M23 with TrustZone is the ideal processor for the most constrained IoT and embedded applications where security is a key requirement.
TrustZone for Armv8-M provides hardware-enforced isolation between the trusted and the untrusted resources on the Cortex-M23 device, while maintaining the efficient exception handling and determinism that have been the hallmark of all Cortex-M processors.
| Architecture | Armv8-M Baseline |
| Bus Interface | AMBA 5 AHB (Von Neumann bus architecture) Optional single cycle I/O interface |
| ISA Support | Thumb/Thumb-2 subset |
| Pipeline | Two-stage |
| Software Security |
Optional TrustZone for Armv8-M with optional security Attribution Unit of up to 8 regions Stack limit checking for Secure stack pointers |
| Memory Protection | Optional Memory Protection Unit (MPU) with up to 16 regions per security state |
| Interrupts | Non-maskable Interrupt (NMI) and up to 240 physical interrupts with 4 priority levels |
| Wake-up Interrupt Controller | Optional for waking up the processor from state retention power gating or when all clocks are stopped |
| Sleep Modes | Integrated WFI and WFE Instructions and Sleep On Exit capability Sleep and Deep Sleep Signals |
| Enhanced Instructions | Hardware single-cycle (32x32) multiply and fast (32/32) divide option |
| Debug | Optional JTAG or Serial Wire Debug ports, up to 4 Breakpoints and 4 Watchpoints |
| Trace | Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM) |
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Characteristics
Performance efficiency 2.64 CoreMark/MHz* and 0.98 DMIPS/MHz**
| Arm Cortex-M23 Implementation Data*** |
||
| 40LP (9-track, typical 0.99V,-40°C) |
28HPC+ (9-track, typical 0.81V, 0°C) |
|
| Dynamic power | 3.86 μW/MHz |
2.26 μW/MHz |
| Floor planned area |
0.0088 mm2 |
0.0037 mm2 |
*See: EEMBC Benchmark Score Viewer
**The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone.
*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.
Cortex-M comparison table
| Feature | Cortex-M0 | Cortex-M0+ | Cortex-M1 | Cortex-M23 | Cortex-M3 | Cortex-M4 | Cortex-M33 | Cortex-M35P | Cortex-M55 |
Cortex-M7 |
| Instruction Set Architecture | Armv6-M | Armv6-M |
Armv6-M |
Armv8-M Baseline |
Armv7-M | Armv7-M |
Armv8-M Mainline |
Armv8-M Mainline |
Armv8.1-M Mainline Helium |
Armv7-M |
| Thumb, Thumb-2 | Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
|
| DMIPS/MHz range* |
0.87-1.27 | 0.95-1.36 | 0.8 |
0.98 | 1.25-1.89 | 1.25-1.95 | 1.5 | 1.5 | 1.6 | 2.14-3.23 |
| CoreMark®/MHz* |
2.33 | 2.46 | 1.85 |
2.64 | 3.34 | 3.42 | 4.02 | 4.02 | 4.2 | 5.01 |
| Pipeline Stages |
3 | 2 | 3 | 2 | 3 | 3 | 3 | 3 | 4 | 6 |
| Memory Protection Unit (MPU) | No | Yes (option) | No | Yes (option) (2 x) |
Yes (option) | Yes (option) | Yes (option) (2 x) |
Yes (option) (2 x) |
Yes (option) (2 x) |
Yes (option) |
| Maximum MPU Regions | 0 | 8 | 0 | 16 | 8 | 8 | 16 | 16 | 16 |
16 |
| Trace (ETM or MTB) | No | MTB (option) | No | MTB (option) or ETMv3 (option) |
ETMv3 (option) | ETMv3 (option) | MTB (option) and/or ETMv4 (option) |
MTB (option) and/or ETMv4 (option) |
ETMv4 (option) |
ETMv4 (option) |
| Digital Signal Processing (DSP) extension |
No | No | No | No | No | Yes | Yes (option) | Yes (option) | Yes (option) |
Yes |
| Floating Point Hardware | No | No | No | No | No | Yes (scalar SP) | Yes (scalar SP) | Yes (scalar SP) | Yes (scalar HP + SP + DP) (vector HP + SP) |
Yes (scalar SP + DP) |
| Systick Timer |
Yes (option) | Yes (option) | Yes (option) | Yes (2 x) | Yes | Yes | Yes (2 x) | Yes (2 x) | Yes (2 x) |
Yes |
| Built-in Caches | No | No | No | No | No | No | No | Yes (option 2- 16kB | Yes (option) |
Yes (option 4-64kB |
| I-cache | I-cache and D-cache |
I-cache, D-cache) | ||||||||
| Tightly Coupled Memory | No | No | Yes | No | No | No | No | No | Yes (option 0-16MB I-TCM/D-TCM) |
Yes (option 0-16MB I-TCM/D-TCM) |
| TrustZone for Armv8-M |
No | No | No | Yes (option) | No | No | Yes (option) | Yes (option) | Yes (option) |
No |
| Coprocessor Interface | No | No | No | No | No | No | Yes (option) | Yes (option) | Yes (option) |
No |
| Bus Protocol |
AHB Lite | AHB Lite, Fast I/O | AHB Lite | AHB5, Fast I/O | AHB Lite, APB | AHB Lite, APB | AHB5, APB | AHB5, APB | AXI5 (main bus), AHB (peripheral bus, TCM slave port and debug) |
AXI4, AHB Lite, APB, TCM |
| Wake-up Interrupt Controller Support |
Yes | Yes | No | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Integrated Interrupt Controller (NVIC) |
Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Maximum # External Interrupts |
32 | 32 | 32 | 240 | 240 | 240 | 480 | 480 | 480 |
240 |
| Hardware Divide | No | No | No | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Single Cycle Multiply |
Yes (option) | Yes (option) | No | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| CMSIS Support |
Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Dual Core Lock-Step Support |
No | No | No | Yes | No | No | Yes | Yes | No |
Yes |
| Arm Custom Instructions |
No |
No |
No |
No |
No |
No |
Yes |
No |
Yes (available in 2021) |
No |
| Common Criteria certification | No | No | No | No | No | No | Yes | Yes | No | No |
*See individual Cortex-M product pages for further information.
SP = Single Precision
DP = Double Precision
HP = Half Precision