Cortex-M23

The Cortex-M23 processor is the smallest and most energy-efficient implementation of the Armv8-M architecture.

Block Diagram on Cortex-M23.

Getting Started

The Cortex-M23 processor is a very compact, two-stage pipelined processor that supports the Armv8-M baseline instruction set. The Cortex-M23 with TrustZone is the ideal processor for the most constrained embedded applications where security is a key requirement. 

TrustZone for Armv8-M provides hardware-enforced isolation between the trusted and the untrusted resources on the Cortex-M23 device, while maintaining the efficient exception handling and determinism that have been the hallmark of all Cortex-M processors. 

Everything you need to know about TrustZone for Armv8-M is here.

Specifications

Architecture Armv8-M Baseline (Von Neumann)
ISA Support Thumb/Thumb-2 subset
Pipeline Two-stage
TrustZone Optional TrustZone for Armv8-M
Memory Protection Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 240 physical interrupts with 4 priority levels
Wake-up Interrupt Controller Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Enhanced Instructions Hardware single-cycle (32x32) multiply and fast (32/32) divide option
Debug Optional JTAG or Serial Wire Debug ports, up to 4 Breakpoints and 4 Watchpoints
Trace Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)

Compare all Cortex-M processors

Characteristics

Performance efficiency 2.50 CoreMark/MHz* and 0.98 DMIPS/Mhz**.

Arm Cortex-M23 implementation data at 40LP (9-track, typical 1.1v, 25°C)
  No TrustZone
With TrustZone
Dynamic Power
 Please contact Arm
 Please contact Arm
Floorplan Area
 Please contact Arm Please contact Arm

* Preliminary data.
** Preliminary data, abides by all of the ground rules laid out in the Dhrystone documentation.

  • Manual containing technical information.

  • Cortex-M23 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M23 processor.

    Read here
  • A program that is running on a desktop.

  • White Paper: Armv8-M Architecture

    Download this White Paper to get a technical overview of the Armv8-M architecture and an introduction to TrustZone security technology.

    Read here
  • A program that is running on a desktop.

  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.

  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz**
 2.33 2.46  1.85
 2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
 3  2  3  2  3  3  3  3  6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) 
Maximum MPU regions  0  8  0  16  8  8  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
 32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
                                                                                                                                                                                                                                                                                                             

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M23 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-M23 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
 Tools
 Software

AMBA System Controllers

CoreLink SIE-200

TrustZone CryptoCell-312

Arm CoreLink CG092

AHB flash cache

Physical IP

DS-5 Development Studio

Arm Keil MDK software development tool

Arm Compiler

Cortex-M Prototyping System

Fast Models

TrustZone for Armv8-M

Cortex Microcontroller Software Interface Standard

Arm Mbed Pelion Device Platform

Community Blogs

Blog post image
After Embedded World: What’s Next for Embedded ML?

There’s no denying that Embedded World (EW) is a whirlwind – 1000 exhibits, 35,000 visitors and over 2,000 industry participants – but now that it’s all over and the dust has settled, I wanted to take a moment to reflect on it...

1 months ago by Dylan Zika
Blog post image
How Arm is powering the road to cleaner smarter vehicles

It’s important to fully understand the requirements of different types of engines, whether it’s a conventional internal combustion engine, hybrid or fully electric powertrain. So, how is Arm powering these different types of vehicles today and how…

1 months ago by James Scobie
Blog post image
Making Helium: Going around in circles (3/4)

The ability to perform computation on data efficiently is only half the story when it comes to new Arm Helium technology. Equally important is the ability to access and store this data in memory.

1 months ago by François Botman
2
Blog post image
Making Helium: Sudoku, registers and rabbits (2/4)

Beatwise execution is at the heart of Helium technology. In the second part of a four-part series, we explore how new M-profile vector extensions efficiently handle different data formats.

2 months ago by Thomas Grocutt
2
Blog post image
Making Helium: Why not just add Neon? (1/4)

Today Arm announced the M‑profile vector extensions (MVE) for the Armv8‑M, which started in Arm’s research group several years ago when we were asked to increase the DSP performance of Arm Cortex‑M processors.

2 months ago by Thomas Grocutt
5
Blog post image
Software building blocks for faster functional safety certification

Arm offers Functional Safety Run-Time System, a set of qualified components for Cortex-M microcontroller​s that lets developers use the highest safety integrity levels for end applications.

2 months ago by Christopher Seidl

Community Forums

Not answered Non-secure code calling secure code - Boot Loaders 0 votes 31 views 0 replies Started 17 hours ago by Jotham Manoranjan Answer this
Suggested answer Interrupts in assembly language
  • Microcontroller
  • Interrupt
 0 votes 76 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer MPIDR and affinity
  • AArch64
 0 votes 60 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Not answered The Peripherals memory map of FVP_BaseR_Cortex-R52x1
  • cortex-r52
  • Fixed Virtual Platforms (FVPs)
  • PrimeCell UART (PL011)
 0 votes 66 views 0 replies Started 3 days ago by Jex1x Answer this
Suggested answer Basic difference between "Generic User Guide" and "Technical Reference Manual"
  • cortex-m0+
 0 votes 134 views 1 replies Latest 3 days ago by 42Bastian Schick Answer this
Suggested answer VMSAv8-64 and spinlock
  • Cortex-A53
  • Cache coherency
  • Cortex-A
  • Baremetal
 0 votes 853 views 3 replies Latest 6 days ago by Ciro Donnarumma Answer this
Not answered Non-secure code calling secure code - Boot Loaders Started 17 hours ago by Jotham Manoranjan 0 replies 31 views
Suggested answer Interrupts in assembly language Latest yesterday by 42Bastian Schick 1 replies 76 views
Suggested answer MPIDR and affinity Latest yesterday by 42Bastian Schick 1 replies 60 views
Not answered The Peripherals memory map of FVP_BaseR_Cortex-R52x1 Started 3 days ago by Jex1x 0 replies 66 views
Suggested answer Basic difference between "Generic User Guide" and "Technical Reference Manual" Latest 3 days ago by 42Bastian Schick 1 replies 134 views
Suggested answer VMSAv8-64 and spinlock Latest 6 days ago by Ciro Donnarumma 3 replies 853 views