Cortex-M23

The Cortex-M23 processor is the smallest and most energy-efficient implementation of the Armv8-M architecture.

Block Diagram on Cortex-M23.

Getting Started

The Cortex-M23 processor is a very compact, two-stage pipelined processor that supports the Armv8-M baseline instruction set. The Cortex-M23 with TrustZone is the ideal processor for the most constrained IoT and embedded applications where security is a key requirement. 

TrustZone for Armv8-M provides hardware-enforced isolation between the trusted and the untrusted resources on the Cortex-M23 device, while maintaining the efficient exception handling and determinism that have been the hallmark of all Cortex-M processors. 

Specifications

Architecture Armv8-M Baseline 
Bus Interface AMBA 5 AHB (Von Neumann)
Optional single cycle I/O interface
ISA Support Thumb/Thumb-2 subset
Pipeline Two-stage
Software Security Optional TrustZone for Armv8-M with optional security
Attribution Unit of up to 8 regions
Stack limit checking for Secure stack pointers
Memory Protection Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 240 physical interrupts with 4 priority levels
Wake-up Interrupt Controller Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Enhanced Instructions Hardware single-cycle (32x32) multiply and fast (32/32) divide option
Debug Optional JTAG or Serial Wire Debug ports, up to 4 Breakpoints and 4 Watchpoints
Trace Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)

Compare all Cortex-M processors

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Characteristics

Performance efficiency 2.64 CoreMark/MHz* and 0.98 DMIPS/MHz**

Arm Cortex-M23 Implementation Data***
  40LP
(9-track, typical 0.99V,
-40°C) 
 28HPC+
(9-track, typical 0.81V, 0°C)
Dynamic Power
 3.86 μW/MHz 
  2.26 μW/MHz 
Floor Planned Area
 0.0088 mm2
 0.0037 mm2

* See product, compiler and compiler flags

** The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug

  • Manual containing technical information.

  • Cortex-M23 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M23 processor.

    Read here
  • A line drawing of a book.

  • Armv8-M Architecture - Technical Overview and Reference Manual

    Access Armv8-M documentation, including the reference manual and an introduction to TrustZone technology.


    Read here
  • A program that is running on a desktop.

  • Cortex-M23 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex‐M23 processor.


    Read here
  • a ulink, a board, a desktop.

  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • A locking device.

  • TrustZone for Armv8-M

    Arm TrustZone technology provides system-wide hardware isolation for trusted software. Learn how to implement TrustZone on Armv8-M processors.

    Read here
  • Systems supporting the main system.

  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here
  • Line drawing of letter, email etc.

  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors.

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
 2.33 2.46  1.85
 2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
 3  2  3  2  3  3  3  3  6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) 
Maximum MPU Regions  0  8  0  16  8  8  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
 32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
 No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M23 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
 Tools
 Software

Corstone Foundation IP

TrustZone CryptoCell-312

Direct Memory Access Controller

Physical IP

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

MPS3

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M23 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Blog post image
Enhancing embedded device security with new TrustZone-enabled microcontroll

The introduction of Nuvoton’s M2351 microcontroller, including the Arm Cortex-M23 processor brings a new level of trust and security to embedded systems.

1 years ago by Kobus Marneweck
1
Blog post image
Microchip 发布首款基于 Arm Cortex-M23 的芯片，引领IoT 设备安全性再上新台阶

试想一下，未来全球将有 1 万亿台联网设备，遍布于汽车、住宅、医院、工作场所、街道，几乎随处可见。如何确保体积小巧的低功耗设备可以验证用户身份，如何确保用户个人信息是被加密处理的，又如何确保电池续航时间足以保证设备安全有效地执行所有功能？ 只有半导体、系统和软件公司采用更安全的技术，市场上才会出现更安全的设备。Microchip 宣布推出第一个基于 Arm Cortex-M23 处理器的芯片系列：SAM L11 和 SAM L10，其中 SAM L11 基于Armv8-M的TrustZone技术

1 years ago by Song Bin 宋斌
Blog post image
Microchip release first Arm Cortex-M23 based chip bringing new levels of…

Microchip unveiled two MCU families, the SAM L11 with TrustZone for Armv8-M, for applications requiring embedded security, and SAM L10 for low-power and touch capabilities.

1 years ago by Kobus Marneweck
Blog post image
Get ready for the IoT race with the new system design kit

Picking the right solution for your next SoC, requires combining lots of different elements together. In order to make this process a little easier, Arm created the Arm Corstone Foundation IP and they are designed to be a complete toolbox for…

1 years ago by Mike EFTIMAKIS
Blog post image
Webinar Q&A - Securing your IoT device with Arm TrustZone for Cortex-M

Securing embedded systems has become a critical task for developers. It is nearly impossible to turn on the news and not hear about yet another major security breach.

1 years ago by Phil Burr
Blog post image
Embedded World Conference 2017 - Software Development in ARMv8-M Architectu

2 years ago by Joseph Yiu
2

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Not answered Is return stack buffer implemented in Zync 7000 Soc Started 10 hours ago by alireza11048 0 replies 13 views
Suggested answer ARMv8 memory ordering Latest 14 hours ago by a.surati 7 replies 1091 views
Not answered gicv3 aarch32 icc_hsre Started yesterday by PJ Nee 0 replies 33 views
Suggested answer NVIC_EnableIRQ : enables only one interrupt at a time? Latest yesterday by Andy Neil 3 replies 73 views
Suggested answer Is there a built-in ARM assembly instruction for the following problem? Latest yesterday by Andy Neil 1 replies 57 views
Suggested answer Is it possible to get keyboard input into an ARM Assembly program? Latest yesterday by Andy Neil 1 replies 49 views