The Cortex-M3 processor is specifically developed for high-performance, low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors.
3x AMBA AHB-Lite interface (Harvard bus architecture)
AMBA ATB interface for CoreSight debug components
|ISA Support||Thumb/Thumb-2 subset
||Optional 8 region MPU with sub regions and background region|
|Bit Manipulation||Integrated Bit-field Processing Instructions and Bus Level Bit Banding
|Interrupts||Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts|
|Interrupt Priority Levels||8 to 256 priority levels
|Wake-up Interrupt Controller
|Enhanced Instructions||Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Adjustment Support
||Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep and Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
||Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints|
|Trace||Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)|
|Reference package or system example
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Performance Efficiency: 3.34 CoreMark/MHz* and 1.25 /1.50 /1.89 DMIPS/MHz**
|Arm Cortex-M3 Implementation Data***
(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
|Dynamic power||141 µW/MHz
|Floor planned area
* See: EEMBC Benchmark Score Viewer
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhryston.
*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.