Cortex-M3

The Arm Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications.

Block Diagram on Cortex-M3.

Getting Started

The Cortex-M3 processor is specifically developed to enable partners to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors.

DesignStart helps companies design innovative custom chips or FPGA designs, with the lowest risk possible. You can access the Cortex-M3 via DesignStart for no upfront fee. 

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Specifications

Architecture Armv7-M Harvard
ISA Support Thumb/Thumb-2
Pipeline three-stage
Memory Protection
Optional 8 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Bit Manipulation Integrated Instructions & Bit Banding
Enhanced Instructions Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math Support
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Trace

Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

Fast access to Cortex-M3

Access Cortex-M3 for $0 upfront for custom chips or FPGA designs with Arm DesignStart.

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Characteristics

Performance Efficiency: 3.34 CoreMark/MHz*  and  1.25 / 1.50 / 1.89 DMIPS/MHz**

Arm Cortex-M3 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power 141 µW/MHz 31 µW/MHz 11 µW/MHz
Floorplanned Area 0.35 mm2 0.09 mm2 0.02 mm2

  * see: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1687&suite=CORE

  ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

   *** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU and debug


  • Manual containing technical information.
  • Cortex-M3 Technical Reference Manual

    For system designers, system integrators, verification engineers and software programmers who are building a Cortex-M3 based SoC.

    Read here
  • A program that is running on a desktop.
  • White Paper: Armv8-M Architecture

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • A guide on software optimization.
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box.

    Learn more
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz**
2.33 2.46  1.85
2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
                                                                                                                                                                                                                                                                                                             

Get support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M3 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-M3 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
Tools
Software

Cortex-M System Design Kit

Socrates System Builder

AMBA System Controllers

DS-5 Development Studio

Arm Keil MDK software development tool

Cortex-M Prototyping System

Cortex Microcontroller Software Interface Standard

Arm Mbed Pelion Device Platform

Software Test Libraries

Community Blogs

Community Forums

Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
0 votes 48 views 2 replies Latest 8 hours ago by Juanea7 Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 35 views 0 replies Started 2 days ago by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
0 votes 847 views 20 replies Latest 4 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 56 views 0 replies Started 4 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 62 views 0 replies Started 4 days ago by BAB Answer this
Not answered Getting processor and cache details
  • cache
  • Linux
0 votes 117 views 0 replies Started 6 days ago by karthikeyan.d Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 8 hours ago by Juanea7 2 replies 48 views
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 2 days ago by jing 0 replies 35 views
Answered Binary Semaphore upset by FIQ Latest 4 days ago by 42Bastian Schick 20 replies 847 views
Not answered Identifying Generic IP Components on an Access Port Started 4 days ago by Torsten Robitzki 0 replies 56 views
Not answered Issue with WatchDog reset De-asserting Started 4 days ago by BAB 0 replies 62 views
Not answered Getting processor and cache details Started 6 days ago by karthikeyan.d 0 replies 117 views