Cortex-M33

The Arm Cortex-M33 processor is the first feature-rich implementation of the Armv8-M architecture. 

Block Diagram on Cortex-M33.

Getting Started

The Cortex-M33 was developed to address all embedded and IoT markets especially those that require efficient security or digital signal control. TrustZone for Armv8-M is the foundation of security for all embedded applications. The processor has many optional features including DSP, a co-processor interface, memory protection units and a floating-point unit. The optional co-processor interface opens the door for customisation and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations. The Cortex-M33 achieves an optimal blend between real time determinism, energy efficiency, software productivity and system security which opens the door for many new applications and opportunities across diverse markets.

Everything you need to know about TrustZone for Armv8-M is here.

Key benefits

  • Provide a security foundation, offering isolation to protect valuable IP and data with TrustZone technology.

  • Extend the processor operation with the tightly coupled co-processor interface.

  • Simplify the design and software development of digital signal control systems with the integrated digital signal processing (DSP) instructions.

  • Accelerate single precision floating-point math operations up to 10x over the equivalent integer software library with the optional floating point-unit.

  • Achieve industry-leading system energy efficiency using the integrated software controlled sleep modes, extensive clock gating, and optional state retention.

Access Cortex-M33 on the Cloud

Prototype software for next generation IoT applications with the full Cortex-M33 feature set with DesignStart FPGA on Cloud.

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Specifications

Architecture Armv8-M Mainline (Harvard)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
TrustZone Optional TrustZone for Armv8-M
DSP Extensions
Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Floating Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Co-processor interface   
Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection
Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller
Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes
Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality.
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM).
Dual Core Lock-Step Support
Yes

Compare all Cortex-M processors

Characteristics

Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS**

Arm Cortex-M33 - Minimum Configuration (28HPC+, 9-track)
Dynamic Power (µW/MHz)**
3.8
Floorplan Area (mm²)
0.014

*Arm Compiler 6.12

Compiler options for CoreMark:

CFlag options = -fomit-frame-pointer -fno-common -Omax -mthumb --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfloat-abi=hard -mfpu=fp-armv8-sp-d16
LFlag options = -Omax

Compiler options for Dhrystone***:

CFlag options = -fomit-frame-pointer -fno-common -fno-inline -fno-lto -Omax -mthumb --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfloat-abi=hard -mfpu=fp-armv8-sp-d16
LFlag options = -Omax --no_lto

Learn about Arm Compiler

**Measured running Dhrystone benchmark.

***Abides by all of the ground rules laid out in the Dhrystone documentation.

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  • Manual containing technical information.
  • Cortex-M33 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M33 processor.

    Read here
  • Manual containing technical information.
  • Cortex-M33 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex‐M33 processor.

    Read here
  • A program that is running on a desktop.
  • White Paper: Armv8-M Architecture

    Download this White Paper to get a technical overview of the Armv8-M architecture and an introduction to TrustZone security technology.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 

 *See individual Cortex-M product pages for further information.

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Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M33 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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Related IP

The Cortex-M33 processor can be incorporated into an SoC using a broad range of Arm technology, including System IP and Physical IP. It is fully supported by development tools from Arm and the world’s #1 embedded ecosystem. Related IP includes:

 

Compatible IP
Tools
Software

Corelink SSE-200 Subsystem

CoreLink SIE-200

TrustZone CryptoCell-312

Cortex-M System Design Kit

AMBA System Controllers

Arm CoreLink CG092 AHB flash cache

CoreLink SDK-200 System Design Kit

Arm Development Studio

Arm Keil MDK software development tool

Arm Compiler

Cortex-M Prototyping System

Fast Models

TrustZone for Armv8-M

Cortex Microcontroller System Interface Standard

Arm Mbed Pelion Device Platform

Community Blogs

Community Forums

Suggested answer Can i change SP at run time in CM33?
  • Arm Development Studio
  • Cortex-M33
  • Armv8-M
0 votes 202 views 3 replies Latest 15 hours ago by Joseph Yiu Answer this
Suggested answer Memory Protection Unit - Complexity in usage 0 votes 520 views 7 replies Latest 16 hours ago by Andy Neil Answer this
Suggested answer Monitor Mode Debug 0 votes 610 views 7 replies Latest 19 hours ago by Andy Neil Answer this
Not answered Audio mixing efficiently and hard realtime requirment
  • algorithms
  • audio
  • Digital Signal Processor (DSP)
  • Cortex-M4
  • STM32 F4
0 votes 69 views 0 replies Started yesterday by Manojkumar Subramaniam Answer this
Not answered Are there any Cortex-M controller with h.264 encoder? 0 votes 67 views 0 replies Started yesterday by Vick Answer this
Answered 32-bit encoding hex values for Arm instructions 0 votes 298 views 3 replies Latest 2 days ago by BQL Answer this
Suggested answer Can i change SP at run time in CM33? Latest 15 hours ago by Joseph Yiu 3 replies 202 views
Suggested answer Memory Protection Unit - Complexity in usage Latest 16 hours ago by Andy Neil 7 replies 520 views
Suggested answer Monitor Mode Debug Latest 19 hours ago by Andy Neil 7 replies 610 views
Not answered Audio mixing efficiently and hard realtime requirment Started yesterday by Manojkumar Subramaniam 0 replies 69 views
Not answered Are there any Cortex-M controller with h.264 encoder? Started yesterday by Vick 0 replies 67 views
Answered 32-bit encoding hex values for Arm instructions Latest 2 days ago by BQL 3 replies 298 views