The Cortex-M33 processor is for IoT and embedded applications that require efficient security or digital signal control.
The processor has many optional features including a DSP extension, TrustZone security for hardware-enforced isolation, a coprocessor interface, memory protection units, and a floating-point unit. The optional coprocessor interface opens the door for customization and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations.
The Cortex-M33 processor with TrustZone and memory protection is certified to EAL6+ for the Common Criteria ISO 15408 standard providing security assurance for applications that require high levels of protection, such as smart cards, SIM cards, and banking cards.
The Cortex-M33 processor achieves an optimal blend between real-time determinism, energy efficiency, software productivity, and system security which opens the door for many new applications and opportunities across diverse markets.
|Architecture||Armv8-M with Mainline extension|
2x AMBA5 AHB (Harvard bus architecture)
|Software Security||Optional TrustZone for Armv8-M, with optional Security Attribution Unit of up to 8 regions
Stack limit checking
||Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
|Floating Point Unit
||Optional single precision floating point unit
IEEE 754 compliant
||Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
||Optional Memory Protection Unit (MPU) with up to 16 regions per security state
|Interrupts||Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
|Wake-up Interrupt Controller
||Optional for waking up the processor from state retention power gating or when all clocks are stopped
||Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality
||Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints|
|Trace||Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)|
|Reference design or system example
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.
Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS/MHz**
|Arm Cortex-M33 Implementation Data***|
(9-track, typical 0.99V, -40°C)
(7-track, typical 0.81V, 0°C)
(7-track, typical 0.72V, 85°C)
||12.0 μW/MHz||3.8 μW/MHz||3.9 μW/MHz|
|Floor plan Area
|| 0.028 mm2
||0.014 mm2||0.008 mm2|
**The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone.
***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug.
Cortex-M comparison table
Download the following PDF datasheet to compare the specifications of Cortex-M processors.