Specifications 

The Cortex-M33 processor is for IoT and embedded applications that require efficient security or digital signal control.

The processor has many optional features including a DSP extension, TrustZone security for hardware-enforced isolation, a coprocessor interface, memory protection units, and a floating-point unit. The optional coprocessor interface opens the door for customization and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations.

The Cortex-M33 processor with TrustZone and memory protection is certified to EAL6+ for the Common Criteria ISO 15408 standard providing security assurance for applications that require high levels of protection, such as smart cards, SIM cards, and banking cards.

The Cortex-M33 processor achieves an optimal blend between real-time determinism, energy efficiency, software productivity, and system security which opens the door for many new applications and opportunities across diverse markets.

Block Diagram for Cortex-M33
Architecture Armv8-M with Mainline extension
Bus Interface 2x AMBA5 AHB (Harvard bus architecture)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
Software Security Optional TrustZone for Armv8-M, with optional Security Attribution Unit of up to 8 regions
Stack limit checking
DSP Extension
Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Floating Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Co-processor interface   
Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection
Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller
Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes
Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)
Reference design or system example
Corstone-201

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Characteristics

Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS/MHz**

Arm Cortex-M33 Implementation Data***
  40LP
(9-track, typical 0.99V, -40°C) 
28HPC+
(7-track, typical 0.81V, 0°C) 
 16FFC
(7-track, typical 0.72V, 85°C)
Dynamic Power 
12.0 μW/MHz   3.8 μW/MHz   3.9 μW/MHz 
Floor plan Area
0.028 mm2
 0.014 mm2  0.008 mm2

*See product, compiler and compiler flags.

**The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug.


Cortex-M comparison table

Download the following PDF datasheet to compare the specifications of Cortex-M processors.

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