Specifications

The Cortex-M33 processor is for IoT and embedded applications that require efficient security or digital signal control. The processor allows programmers to easily achieve software isolation, by protecting almost any asset from specific attacks with Arm TrustZone technology.

The processor has many optional features including a DSP extension, a co-processor interface, memory protection units and a floating-point unit. The optional co-processor interface opens the door for customization and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations.

The Cortex-M33 achieves an optimal blend between real-time determinism, energy efficiency, software productivity and system security which opens the door for many new applications and opportunities across diverse markets.

Block Diagram on Cortex-M33.
Architecture Armv8-M with Mainline extension
Bus Interface 2x AMBA5 AHB (Harvard bus architecture)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
Software Security Optional TrustZone for Armv8-M, with optional Security Attribution Unit of up to 8 regions
Stack limit checking
DSP Extension
Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Floating Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Co-processor interface   
Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection
Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller
Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes
Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

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Characteristics

Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS/MHz**

Arm Cortex-M33 Implementation Data***
  40LP
(9-track, typical 0.99V, -40°C) 
28HPC+
(7-track, typical 0.81V, 0°C) 
 16FFC
(7-track, typical 0.72V, 85°C)
Dynamic Power 
12.0 μW/MHz   3.8 μW/MHz   3.9 μW/MHz 
Floor plan Area
0.028 mm2
 0.014 mm2  0.008 mm2

*See product, compiler and compiler flags.

**The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug.


Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision