Cortex-M33

The Arm Cortex-M33 processor is one of the first feature-rich implementations of the Armv8-M architecture. 

Block Diagram on Cortex-M33.

Getting Started

The Cortex-M33 processor is for IoT and embedded applications that require efficient security or digital signal control. The processor allows programmers to easily achieve software isolation, by protecting almost any asset from specific attacks with Arm TrustZone technology.

The processor has many optional features including a DSP extension, a co-processor interface, memory protection units and a floating-point unit. The optional co-processor interface opens the door for customization and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations.

The Cortex-M33 achieves an optimal blend between real-time determinism, energy efficiency, software productivity and system security which opens the door for many new applications and opportunities across diverse markets.

Specifications

Architecture Armv8-M with Mainline extension
Bus Interface 2x AMBA5 AHB (Harvard bus architecture)
APB interface for CoreSight debug components
ISA Support Thumb/Thumb-2
Pipeline Three-stage
Software Security Optional TrustZone for Armv8-M, with optional Security Attribution Unit of up to 8 regions
Stack limit checking
DSP Extension
Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Floating Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Co-processor interface   
Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection
Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller
Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes
Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

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Characteristics

Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS/MHz**

 Arm Cortex-M33 Implementation Data***
  40LP
(9-track, typical 0.99V, -40°C) 
28HPC+
(7-track, typical 0.81V, 0°C) 
 16FFC
(7-track, typical 0.72V, 85°C)
Dynamic Power 
12.0 μW/MHz   3.8 μW/MHz   3.9 μW/MHz 
Floorplan Area
0.028 mm2
 0.014 mm2  0.008 mm2

*See product, compiler and compiler flags.

**The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug


  • Manual containing technical information.
  • Cortex-M33 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M33 processor.

    Read here
  • Models used for applications on a computer.
  • Cortex-M33 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex‐M33 processor.

    Read here
  • A program that is running on a desktop.
  • Armv8-M Architecture - Technical Overview and Reference Manual

    Access Armv8-M documentation including the reference manual and an introduction to TrustZone technology.


    Read here
  • a ulink, a board, a desktop.
  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • A guide on software optimization.
  • DSP Extension

    DSP extension to the Thumb instruction set improves the performance of numerical algorithms. They provide the opportunity to perform signal processing operations directly on the Cortex-M33.

    Read here
  • A locking device.
  • TrustZone for Armv8-M

    Arm TrustZone technology provides system-wide hardware isolation for trusted software. Learn how to implement TrustZone on Armv8-M processors.

    Read here
  • Systems supporting the main system.
  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here
  • A cloud with a lock in front.
  • Access Cortex-M33 on the cloud

    Get instant and free access to a complete reference platform for software development on the Cortex-M33.

    Read more

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M33 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by development tools from Arm and the Arm ecosystem . Related IP includes:

 

Compatible IP
Tools
Software

Corstone Foundation IP

TrustZone CryptoCell-312

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

Arm MPS3 FPGA Prototyping Board 

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M33 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Answered How to do the ARM state change between 64-bit and 32-bit?
  • 32-bit
  • AArch64
  • Armv8-A
  • 64-bit
  • AArch32
0 votes 17385 views 9 replies Latest yesterday by murphy Answer this
Suggested answer ARMv8 memory ordering
  • Cortex-A53
  • Armv8-A
0 votes 947 views 3 replies Latest yesterday by a.surati Answer this
Suggested answer Fail to connect with CM0DSEvel
  • Cortex-M0
  • DesignStart
0 votes 229 views 2 replies Latest 2 days ago by RickyChen Answer this
Answered How to specify virtual Address for pl011 uart in linux kernel
  • APB Peripherals
  • Arm11
  • PrimeCell UART (PL011)
  • Interrupt
0 votes 5484 views 9 replies Latest 2 days ago by barrysingh101 Answer this
Suggested answer Character recognition using NXP LPC1768 (Cortex-M3)
  • Neural Network
  • Cortex-M3
  • Arm NN
0 votes 345 views 3 replies Latest 2 days ago by Andy Neil Answer this
Suggested answer Cortex M0 Vector Table and Bootloading
  • Cortex-M0
  • Interrupt Handling
0 votes 274 views 1 replies Latest 2 days ago by Trampas Answer this
Answered How to do the ARM state change between 64-bit and 32-bit? Latest yesterday by murphy 9 replies 17385 views
Suggested answer ARMv8 memory ordering Latest yesterday by a.surati 3 replies 947 views
Suggested answer Fail to connect with CM0DSEvel Latest 2 days ago by RickyChen 2 replies 229 views
Answered How to specify virtual Address for pl011 uart in linux kernel Latest 2 days ago by barrysingh101 9 replies 5484 views
Suggested answer Character recognition using NXP LPC1768 (Cortex-M3) Latest 2 days ago by Andy Neil 3 replies 345 views
Suggested answer Cortex M0 Vector Table and Bootloading Latest 2 days ago by Trampas 1 replies 274 views