Cortex-M35P

Specifications

Compare all Cortex-M processors

Key technical features

Cortex-M35P extends the anti-tampering features of the SecurCore family of processors, making this state-of-the art technology available to Cortex-M developers. Robust embedded security is more accessible than ever with the benefits of both physical and software security, using the optional TrustZone isolation.

Resilience against physical attacks

When the value of the protected assets is high, then hackers will resort to physical attacks on the device. The processor is built with multiple elements to protect from and detect such attacks.

TrustZone for Armv8-M

A foundation for security for embedded devices. TrustZone offers software isolation to code, memory and I/O while retaining the requirements of embedded applications: real-time deterministic response, minimal switching overhead, and ease of software development.

Interested in learning how to program Secure and Non-secure domains on a processor with TrustZone?

• Watch this webinar recording

• View the webinar slide deck

• See the webinar Q&A

Explore more resources and get your questions answered on our TrustZone for Armv8-M Community.

Instruction cache

An integrated cache improves performance when running from embedded flash. The cache is resilient to physical attacks. The user can modify the customizable cache parity into an ECC (error correcting code) for safety applications.

Co-processor interface

A dedicated bus for extending the operation of the processor with tightly coupled co-processors to handle frequent and compute intensive operations in an ecosystem friendly manner. The interface supports up to eight accelerators and takes into account the security state of the co-processor.

Digital Signal Processing (DSP), SIMD, saturating arithmetic, fast MAC

Powerful instruction set for accelerating DSP applications, built right into the processor. A highly optimized DSP library built using these instructions is available free-of-charge from the Arm website (CMSIS Library).

Memory Protection Unit (MPU)

Software reliability and system security improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data. Each of the security zones can have a dedicated MPU that may be configured with a different number of regions. Programming the regions is easier, removing the constraint to align regions on power-of-two size.

Integrated Nested Vectored Interrupt Controller (NVIC)

There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.

Powerful debug and non-intrusive real-time trace

Comprehensive debug and trace features dramatically improve developer productivity. Debug support and cycle accurate non-intrusive instruction and data trace for all stages of development supports high stakes secure projects as they move through development lifecycle.

The Cortex-M35P processor achieves an optimal blend between real-time determinism, energy efficiency, software productivity and a robust security foundation, using isolation to protect valuable IP and data with TrustZone technology and physical security.

Cortex-M Comparison Table

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M35P processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Related IP and tools

The Cortex-M35P processor can be incorporated into an SoC using a broad range of Arm technology, including system IP and physical IP, speeding up time to market and optimizing implementation. It is fully supported by development tools from Arm and the world’s #1 embedded ecosystem.

Related IP and tools include: