A Cortex-M processor with physical security features and optional software isolation using TrustZone for Armv8-M.

For embedded developers seeking to hinder physical tampering and achieve a higher level of security certification, Arm offers the Cortex-M35P: a robust, high-performing processor. It builds upon the proven Arm Cortex-M technology deployed in billions of SoCs, making physical and software security accessible for all developers. 

Cortex-M35P with physical security features, memory protection, and TrustZone security for hardware-enforced isolation is certified to EAL6+ for the Common Criteria ISO 15408 standard, one of the most stringent security evaluation methodologies. This certification helps SoC designers develop products with as much security assurance as possible.

Cortex-M35P Block Diagram

Arm Cortex-M35P processor

Architecture Armv8-M with Mainline extension
Bus Interface  2x AMBA5 AHB (Harvard bus architecture)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
Software Security Optional TrustZone for Armv8-M, with optional Security Attribution Unit of up to 8 regions
Stack limit checking
Physical Security Built-in protection from invasive and non-invasive attacks
DSP Extensions Optional DSP/SIMD instructions Single cycle 16/32-bit MAC Single cycle dual 16-bit MAC 8/16-bit SIMD arithmetic
Floating Point Unit Optional single precision floating point unit IEEE 754 compliant
Co-processor Interface Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-Maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes Integrated Wait for Event (WFE) and Wait for Interrupt (WFI) instructions with Sleep On Exit functionality
Debug Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)
Cache Instruction cache
Dual Core Lock-Step Support (DCLS)
Yes, DCLS configuration


Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS/MHz**

 Arm Cortex-M35P Implementation Data***
(7-track, typical 0.99V, -40°C) 
(7-track, typical 0.81V, 0°C) 
(9-track, typical 0.72V, 0°C)
Dynamic Power 
14.7 μW/MHz   9.2 μW/MHz   5.1 μW/MHz 
Floor Planned Area
0.091 mm2
 0.034 mm2  0.021 mm2

*Arm Compiler 6.12 Flags Cortex-M35P --fpu=FPv5-SP.

**The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug.

Cortex-M comparison table

Download the following PDF datasheet to compare the specifications of Cortex-M processors.