Cortex-M3

The Arm Cortex-M3 processor is a popular 32-bit processor for highly deterministic real-time applications.

Block Diagram on Cortex-M3.

Getting Started

The Cortex-M3 processor is specifically developed for high-performance, low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors.

Specifications

Architecture Armv7-M
Bus Interface 3x AHB-Lite interface (Harvard bus architecture)
APB interface for CoreSight debug components
ISA Support Thumb/Thumb-2 subset
Pipeline Three-stage
Memory Protection
Optional 8 region MPU with sub regions and background region
Bit Manipulation Integrated Bit-field Processing Instructions & Bus Level Bit Banding
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Optional
Enhanced Instructions Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Adjustment Support
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

Start designing with Cortex-M3

Cortex-M3 is available to access for $0 upfront for prototyping and commercializing a custom SoC with Arm DesignStart. Alternatively, if you would like to design with Cortex-M3 and additional Arm IP, Arm Flexible Access delivers unlimited design access to a wide range of IP products, support, tools and training – with payment due only at the point of manufacture.

Characteristics

Performance Efficiency: 3.34 CoreMark/MHz* and 1.25 /1.50 /1.89 DMIPS/MHz**

Arm Cortex-M3 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power 141 µW/MHz 31 µW/MHz 11 µW/MHz
Floorplanned Area 0.35 mm2 0.09 mm2 0.02 mm2

 * See: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1687&suite=CORE

  ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

   *** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug


  • Manual containing technical information.
  • Cortex-M3 Technical Reference Manual

    For system designers, system integrators, verification engineers and software programmers who are building a Cortex-M3 based SoC.

    Read here
  • A program that is running on a desktop.
  • Cortex-M3 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex-M3 processor.

    Read here
  • A guide on software optimization.
  • Armv7-M Architecture Reference Manual

    This manual describes the instruction set, memory model, and programmers' model for Armv7-M compliant processors.

    Read here
  • a ulink, a board, a desktop.
  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors. 

    Read here
  • Systems supporting the main system.
  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here
  • Line drawing of letter, email etc.
  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors.

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M3 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK software development tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Get support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M3 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Suggested answer ARMv8 memory ordering
  • Cortex-A53
  • Armv8-A
0 votes 985 views 4 replies Latest 11 hours ago by roffelsen Answer this
Suggested answer Unable to Download Code to Controller
  • 5 (BusFault)
  • 3 (HardFault)
  • 6 (UsageFault)
  • Cortex-M4
0 votes 404 views 8 replies Latest 20 hours ago by ShivasWorld Answer this
Suggested answer Character recognition using NXP LPC1768 (Cortex-M3)
  • Neural Network
  • Cortex-M3
  • Arm NN
0 votes 378 views 4 replies Latest 20 hours ago by 42Bastian Schick Answer this
Suggested answer Calling non-secure Reset Handler from Secure main
  • Cortex-M33
  • Armv8-M
0 votes 312 views 1 replies Latest yesterday by Radhika Raghavendran Answer this
Suggested answer SAU configuration failure
  • TrustZone for Armv8-M
  • Cortex-M33
0 votes 164 views 1 replies Latest yesterday by Radhika Raghavendran Answer this
Answered How to do the ARM state change between 64-bit and 32-bit?
  • 32-bit
  • AArch64
  • Armv8-A
  • 64-bit
  • AArch32
0 votes 17458 views 9 replies Latest 2 days ago by murphy Answer this
Suggested answer ARMv8 memory ordering Latest 11 hours ago by roffelsen 4 replies 985 views
Suggested answer Unable to Download Code to Controller Latest 20 hours ago by ShivasWorld 8 replies 404 views
Suggested answer Character recognition using NXP LPC1768 (Cortex-M3) Latest 20 hours ago by 42Bastian Schick 4 replies 378 views
Suggested answer Calling non-secure Reset Handler from Secure main Latest yesterday by Radhika Raghavendran 1 replies 312 views
Suggested answer SAU configuration failure Latest yesterday by Radhika Raghavendran 1 replies 164 views
Answered How to do the ARM state change between 64-bit and 32-bit? Latest 2 days ago by murphy 9 replies 17458 views