The Arm Cortex-M4 processor is a highly-efficient embedded processor. 

The Cortex-M4 processor is developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors satisfies many markets. These industries include motor control, automotive, power management, embedded audio and industrial automation markets.

Block Diagram on Cortex-M4.

Arm Cortex-M4 processor

Architecture Armv7E-M
Bus Interface 3x AMBA AHB-Lite interface (Harvard bus architecture)
AMBA ATB interface for CoreSight debug components
ISA Support Thumb/Thumb-2
Pipeline 3-stage + branch speculation
DSP Extension
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Memory Protection
Optional 8 region MPU with sub regions and background region
Bit Manipulation
Integrated Bit Field Processing Instructions & Bus Level Bit Banding
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)
Reference package or system example Corstone-101

Compare the specifications of Cortex-M processors:
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Performance Efficiency: 3.54 CoreMark/MHz* and with FPU: 1.26 /1.67 /3.65 DMIPS/MHz**

Arm Cortex-M4 Implementation Data***

(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 85°C)
Dynamic Power 151 µW/MHz 32.82 µW/MHz 12.26 µW/MHz
Floor plan Area 0.44 mm2 0.119 mm2 0.028 mm2

 See product, compiler and compiler flags

 ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone. Arm Compiler 6.17

 *** Base usable configuration includes DSP extensions, 1 IRQ + NMI, excludes ETM, MPU, FPU  and debug