Cortex-M4

The Arm Cortex-M4 processor is a highly-efficient embedded processor. 

Block Diagram on Cortex-M4.

Getting Started

The Cortex-M4 processor is developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors satisfies many markets. These industries include motor control, automotive, power management, embedded audio and industrial automation markets.


Specifications

Architecture Armv7E-M
Bus Interface 3x AMBA AHB-Lite interface (Harvard bus architecture)
AMBA ATB interface for CoreSight debug components
ISA Support Thumb/Thumb-2
Pipeline 3-stage + branch speculation
DSP Extension
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Memory Protection
Optional 8 region MPU with sub regions and background region
Bit Manipulation
Integrated Bit Field Processing Instructions & Bus Level Bit Banding
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Optional
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

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Characteristics

Performance Efficiency: 3.42 CoreMark/MHz* and without FPU: 1.25 /1.52 /1.91 DMIPS/MHz**, with FPU: 1.27 /1.55 /1.95 DMIPS/MHz**

Arm Cortex-M4 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 85°C)
Dynamic Power 151 µW/MHz 32.82 µW/MHz 12.26 µW/MHz
Floor plan Area 0.44 mm2 0.119 mm2 0.028 mm2

 See product, compiler and compiler flags

 ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

 *** Base usable configuration includes DSP extensions, 1 IRQ + NMI, excludes ETM, MPU, FPU  and debug


Related IP

The Cortex-M4 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

CoreLink AHB Cache

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M55
Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv8.1-M Mainline
Helium
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5   1.6 2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02  4.2 5.01
Pipeline Stages
 4
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) (2 x)
Yes (option) 
Maximum MPU Regions  16  16  16  16
16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
ETMv4 (option)
Digital Signal Processing (DSP) extension
No  No  No  No  No Yes  Yes (option) Yes (option)  Yes (option)
Yes 
Floating Point Hardware  No No  No  No  No Yes (scalar SP) Yes (scalar SP) Yes (scalar SP) Yes (scalar HP +
SP + DP) (vector
HP + SP)
Yes (scalar SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes (2 x)
Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option)
Yes (option 4-64kB 
 I-cache I-cache and D-cache
I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM)
Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  Yes (option)
No 
Coprocessor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  Yes (option)
No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI5 (main bus), AHB
(peripheral bus,
TCM slave port and debug)
AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 480
240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes
Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  No
Yes 
Arm Custom Instructions
No
No
No
No
No
No
Yes
No
Yes (available in 2021)
No
Common Criteria certification No No  No  No  No  No  Yes  Yes  No No 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision

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Suggested answer Which bit fields are for Cortex-M4F SCB_ICSR.VECTORPENDING Latest yesterday by 42Bastian Schick 1 replies 94 views
Suggested answer Tasks can't switch to others, always run at OSStartHang. but whitout boot code ,the app can run ok. the core of the chip is cortex-M0 Latest 3 days ago by John_shi 7 replies 2859 views
Not answered SVCall returning to 0xdeadbeee Started 3 days ago by DanS 0 replies 168 views
Not answered How to test L1/L2 cache? Started 3 days ago by Zhiping Jiang 0 replies 350 views
Not answered V2C-DAPLINK-035A shield schematic Started 4 days ago by Brix 0 replies 53 views
Answered Speculative execution/loads on Cortex-A5 Latest 4 days ago by vstehle 5 replies 1530 views