Cortex-M4

The Arm Cortex-M4 processor is a highly-efficient embedded processor. 

Block Diagram on Cortex-M4.

Getting Started

The Cortex-M4 processor is developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors satisfies many markets. These industries include motor control, automotive, power management, embedded audio and industrial automation markets.

Specifications

Architecture Armv7E-M
Bus Interface 3x AMBA AHB-Lite interface (Harvard bus architecture)
AMBA ATB interface for CoreSight debug components
ISA Support Thumb/Thumb-2
Pipeline 3-stage + branch speculation
DSP Extension
 Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
 Optional single precision floating point unit
IEEE 754 compliant
Memory Protection
 Optional 8 region MPU with sub regions and background region
Bit Manipulation
 Integrated Bit Field Processing Instructions & Bus Level Bit Banding
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
 Optional
Sleep Modes
 Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
 Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

Characteristics

Performance Efficiency: 3.42 CoreMark/MHz* and without FPU: 1.25 /1.52 /1.91 DMIPS/MHz**, with FPU: 1.27 /1.55 /1.95 DMIPS/MHz**

Arm Cortex-M4 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
 90LP
(7-track, typical 1.2v, 25°C)		 40LP
(9-track, typical 1.1v, 85°C)
Dynamic Power 151 µW/MHz 32.82 µW/MHz 12.26 µW/MHz
Floor plan Area 0.44 mm2 0.119 mm2 0.028 mm2

 * See product, compiler and compiler flags

 ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

 *** Base usable configuration includes DSP extensions, 1 IRQ + NMI, excludes ETM, MPU, FPU  and debug

Related IP

The Cortex-M4 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
 Tools
 Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

CoreLink AHB Cache

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M
Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M55
 Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv8.1-M Mainline
Helium
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.98 1.25-1.89  1.25-1.95  1.5  1.5   1.6 2.14-3.23
CoreMark®/MHz*
 2.33 2.46  1.85
 2.64 3.34 3.42  4.02 4.02  4.2 5.01
Pipeline Stages
 3  2  3  2  3  3  3  3   4 6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) (2 x)
 Yes (option) 
Maximum MPU Regions  0  8  0  16  8  8  16  16  16
 16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
 ETMv4 (option)
Digital Signal Processing (DSP) extension
 No  No  No  No  No Yes  Yes (option) Yes (option)  Yes (option)
 Yes 
Floating Point Hardware  No No  No  No  No Yes (scalar SP) Yes (scalar SP) Yes (scalar SP) Yes (scalar HP +
SP + DP) (vector
HP + SP)
 Yes (scalar SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes (2 x)
 Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option)
 Yes (option 4-64kB 
 I-cache I-cache and D-cache
 I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM)
 Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  Yes (option)
 No 
Coprocessor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  Yes (option)
No 
Bus Protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI5 (main bus), AHB
(peripheral bus,
TCM slave port and debug)
 AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes
 Yes 
Integrated Interrupt Controller (NVIC)
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes  Yes 
Maximum # External Interrupts
 32  32  32  240  240  240  480 480 480
 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes
 Yes 
Single Cycle Multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes
 Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes
 Yes 
Dual Core Lock-Step Support
 No No No Yes  No No Yes Yes  No
 Yes 
Arm Custom Instructions
 No
 No
 No
 No
 No
 No
 Yes
 No
 Yes (available in 2021)
 No
Common Criteria certification No No  No  No  No  No  Yes  Yes  No No 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision

Get Support

Community Blogs

Blog post image
Implementing Embedded Continuous Integration with Jenkins and Docker: Part

After reading through this blog series, you and your team will be armed with the knowledge to create a customized, consistent, and automated embedded software development workflow.

1 years ago by Zach Lasiuk
1
Blog post image
Teaching Scratchy to Walk with Neural Networks

What would you do with a Cortex-M4, a neural network, some Lego and cable ties? Sebastian Förster built a small, four-legged robot and taught it to walk.

2 years ago by Hellen Norman
Blog post image
How to effectively utilize continuous integration, for SoC software devs

In this article I tackle the classic question engineers developing software on custom SoCs grapple with constantly: “How do I test my software before the hardware team gets me a working silicon chip?"

2 years ago by Zach Lasiuk
Blog post image
Whitepaper: How automotive body electronics are changing

What is driving automotive body electronics to move from 16 to 32 bit architectures?

2 years ago by Eoin McCann
2
Blog post image
EW day 2 blog: All about automotive

As embedded devices become more prevalent and assume more responsibility in our daily lives, there is a need for functional safety to make sure that we are not put in danger by any faults that may occur.

3 years ago by Eoin McCann
Blog post image
Automotive electronics design takes a giant leap forward

The trickle-down effect from increased government regulations and from car consumers’ embrace of automotive electronics is far-reaching. These consequences challenge engineering teams more and more. Think about the shift from 8- and 16-bit micr

3 years ago by Brian Fuller

Community Forums

Suggested answer translation table APTable permission problem
  • Cortex-A57
  • Armv8-A
  • Linux
 0 votes 264 views 2 replies Latest 18 hours ago by raks8877 Answer this
Not answered Regarding Visibility of Multi Master ACE-Lite System 0 votes 231 views 0 replies Started yesterday by RajaAC Answer this
Not answered Cortex-M3 softcore minimal SoC
  • Cortex-M3
  • DesignStart
 0 votes 41 views 0 replies Started yesterday by TinyLabs Answer this
Not answered Bus Fault when configuring cross trigger matrix / CTICONTROL 0 votes 93 views 0 replies Started yesterday by Jacek Wywrót Answer this
Answered which is better for performance fetching instructions from flash or SRAM? 0 votes 301 views 4 replies Latest 2 days ago by Andy Neil Answer this
Suggested answer the linux kernel will be hung here as long as there are more than one core inside one cluster 0 votes 4962 views 1 replies Latest 3 days ago by Zhifei Yang Answer this
Suggested answer translation table APTable permission problem Latest 18 hours ago by raks8877 2 replies 264 views
Not answered Regarding Visibility of Multi Master ACE-Lite System Started yesterday by RajaAC 0 replies 231 views
Not answered Cortex-M3 softcore minimal SoC Started yesterday by TinyLabs 0 replies 41 views
Not answered Bus Fault when configuring cross trigger matrix / CTICONTROL Started yesterday by Jacek Wywrót 0 replies 93 views
Answered which is better for performance fetching instructions from flash or SRAM? Latest 2 days ago by Andy Neil 4 replies 301 views
Suggested answer the linux kernel will be hung here as long as there are more than one core inside one cluster Latest 3 days ago by Zhifei Yang 1 replies 4962 views