Cortex-M4

The Arm Cortex-M4 processor is a highly-efficient embedded processor. 

Block Diagram on Cortex-M4.

Getting Started

The Cortex-M4 processor is developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors satisfies many markets. These industries include motor control, automotive, power management, embedded audio and industrial automation markets.


Specifications

Architecture Armv7E-M
Bus Interface 3x AHB Lite interface (Harvard bus architecture)
APB interface for CoreSight debug components
ISA Support Thumb/Thumb-2
Pipeline 3-stage + branch speculation
DSP Extension
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Memory Protection
Optional 8 region MPU with sub regions and background region
Bit Manipulation
Integrated Bit Field Processing Instructions & Bus Level Bit Banding
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Optional
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

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Characteristics

Performance Efficiency: 3.42 CoreMark/MHz* and without FPU: 1.25 /1.52 /1.91 DMIPS/MHz**, with FPU: 1.27 /1.55 /1.95 DMIPS/MHz**

Arm Cortex-M4 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 85°C)
Dynamic Power 151 µW/MHz 32.82 µW/MHz 12.26 µW/MHz
Floor plan Area 0.44 mm2 0.119 mm2 0.028 mm2

 See product, compiler and compiler flags

 ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

 *** Base usable configuration includes DSP extensions, 1 IRQ + NMI, excludes ETM, MPU, FPU  and debug


  • Manual containing technical information.
  • Cortex-M4 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M4 processor.

    Read here
  • A program that is running on a desktop.
  • Cortex-M4 Devices Generic User Guide

    For application and system-level developers, the Devices Generic User Guide provides programming information for the Cortex-M4 processor.

    Read here
  • A guide on software optimization.
  • Armv7-M Architecture Reference Manual

    This manual describes the instruction set, memory model, and programmers' model for Armv7-M compliant processors.

    Read here
  • a ulink, a board, a desktop.
  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • Systems supporting the main system.
  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here
  • A guide on software optimization.
  • DSP Extension

    DSP extension to the Thumb instruction set improves the performance of numerical algorithms. They provide the opportunity to perform signal processing operations directly on the Cortex-M4.

    Read here
  • Line drawing of letter, email etc.
  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors.

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M4 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK Software Development Tool

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M4 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered How do I install an SSL certificate on a Tableau server?
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0 votes 50 views 0 replies Started yesterday by mounika123 Answer this
Not answered Cortex-M3 frequency 0 votes 57 views 0 replies Started yesterday by Sorush Answer this
Suggested answer Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?
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  • Armv8-A
  • System MMU
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Suggested answer Setting PC for and waking up secondary cores from the primary core
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Not answered How to generate an address size fault? 0 votes 62 views 0 replies Started 2 days ago by ohskr27 Answer this
Answered Unaligned accesses - CMSDK Example Cortex M0
  • Cortex-M0
0 votes 570 views 8 replies Latest 3 days ago by eugch Answer this
Not answered How do I install an SSL certificate on a Tableau server? Started yesterday by mounika123 0 replies 50 views
Not answered Cortex-M3 frequency Started yesterday by Sorush 0 replies 57 views
Suggested answer Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"? Latest 2 days ago by jhoney 3 replies 3837 views
Suggested answer Setting PC for and waking up secondary cores from the primary core Latest 2 days ago by jhoney 12 replies 5440 views
Not answered How to generate an address size fault? Started 2 days ago by ohskr27 0 replies 62 views
Answered Unaligned accesses - CMSDK Example Cortex M0 Latest 3 days ago by eugch 8 replies 570 views