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Webinar: Technical Overview of the Cortex-M55 and Ethos-U55 Processors
Arm Cortex-M55 and Ethos-U55 processors blog
How to port TensorFlow Lite for Microcontroller applications to the Cortex-M55 blog
Start prototyping with the Corstone-300 FVP including Cortex-M55 available at no cost before silicon availability blog
Software development for Cortex-M55
Cortex-M55 Training
Cortex-M resources
The Arm Cortex-M55 processor is Arm’s most AI-capable Cortex-M processor and the first to feature Arm Helium vector processing technology. It brings energy-efficient digital signal processing (DSP) and machine learning (ML) capabilities to the Cortex-M family. With the Cortex-M55 processor, developers can take advantage of the ease-of-use of Cortex-M, a single toolchain, optimized software libraries, and an industry-leading embedded ecosystem. The processor allows the integration of differentiating AI techniques, while staying within the system cost and energy constraints of battery powered IoT devices.
| Architecture | Armv8.1-M |
| Bus interface | AMBA 5 AXI5 64-bit master (compatible to AXI4 IPs) |
| Pipeline | 4-stage (for main integer pipeline) |
| Security | Arm TrustZone technology (optional) |
| DSP extension |
32-bit DSP/SIMD extension |
| M-Profile Vector Extension (MVE) | Helium (optional) |
| Floating-point Unit (FPU) |
Optional |
| Coprocessor interface |
64-bit (optional) |
| Instruction cache |
Up to 64KB with ECC (optional) |
| Data cache |
Up to 64KB with ECC (optional) |
| Instruction TCM (ITCM) |
Up to 16MB with ECC (optional) |
| Data TCM (DTCM) |
Up to 16MB with ECC (optional) |
| Interrupts |
Up to 480 interrupts + Non-maskable interrupt (NMI) |
| Wake-up Interrupt Controller (WIC) | Internal and/or external (optional) |
| Multiply-accumulate (MAC) / cycle |
Up to: 2 x 32-bit MACs/cycle 4 x 16-bit MACs/cycle 8 x 8-bit MACs/cycle |
| Sleep modes |
Multiple power domains Sleep modes (sleep and deep sleep) Sleep-on-exit Optional retention support for memories and logic |
| Debug |
Hardware and software breakpoints Performance Monitoring Unit (PMU) |
| Trace | Optional Instruction trace with Embedded Trace Macrocell (ETM), Data Trace (DWT) (selective data trace), and Instrumentation Trace (ITM) (software trace) |
| Arm Custom Instructions |
Optional (available in 2021) |
| Robustness |
ECC on instruction cache, data cache, instruction TCM, data TCM (optional) Bus interface protection (optional) PMC-100 (Programmable MBIST Controller, optional) Reliability, availability and serviceability (RAS) extension |
Performance efficiency 4.2 CoreMark/MHz* and 1.6 DMIPS/MHz*.
*Please contact Arm for compilation conditions, as well as implementation data.
| Feature | Cortex-M0 | Cortex-M0+ | Cortex-M1 | Cortex-M23 | Cortex-M3 | Cortex-M4 | Cortex-M33 | Cortex-M35P | Cortex-M55 |
Cortex-M7 |
| Instruction Set Architecture | Armv6-M | Armv6-M |
Armv6-M |
Armv8-M Baseline |
Armv7-M | Armv7-M |
Armv8-M Mainline |
Armv8-M Mainline |
Armv8.1-M Mainline Helium |
Armv7-M |
| Thumb, Thumb-2 | Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
Thumb, Thumb-2 |
|
| DMIPS/MHz range* |
0.87-1.27 | 0.95-1.36 | 0.8 |
0.98 | 1.25-1.89 | 1.25-1.95 | 1.5 | 1.5 | 1.6 | 2.14-3.23 |
| CoreMark®/MHz* |
2.33 | 2.46 | 1.85 |
2.64 | 3.34 | 3.42 | 4.02 | 4.02 | 4.2 | 5.01 |
| Pipeline Stages |
3 | 2 | 3 | 2 | 3 | 3 | 3 | 3 | 4 | 6 |
| Memory Protection Unit (MPU) | No | Yes (option) | No | Yes (option) (2 x) |
Yes (option) | Yes (option) | Yes (option) (2 x) |
Yes (option) (2 x) |
Yes (option) (2 x) |
Yes (option) |
| Maximum MPU Regions | 0 | 8 | 0 | 16 | 8 | 8 | 16 | 16 | 16 |
16 |
| Trace (ETM or MTB) | No | MTB (option) | No | MTB (option) or ETMv3 (option) |
ETMv3 (option) | ETMv3 (option) | MTB (option) and/or ETMv4 (option) |
MTB (option) and/or ETMv4 (option) |
ETMv4 (option) |
ETMv4 (option) |
| Digital Signal Processing (DSP) extension |
No | No | No | No | No | Yes | Yes (option) | Yes (option) | Yes (option) |
Yes |
| Floating Point Hardware | No | No | No | No | No | Yes (scalar SP) | Yes (scalar SP) | Yes (scalar SP) | Yes (scalar HP + SP + DP) (vector HP + SP) |
Yes (scalar SP + DP) |
| Systick Timer |
Yes (option) | Yes (option) | Yes (option) | Yes (2 x) | Yes | Yes | Yes (2 x) | Yes (2 x) | Yes (2 x) |
Yes |
| Built-in Caches | No | No | No | No | No | No | No | Yes (option 2- 16kB | Yes (option) |
Yes (option 4-64kB |
| I-cache | I-cache and D-cache |
I-cache, D-cache) | ||||||||
| Tightly Coupled Memory | No | No | Yes | No | No | No | No | No | Yes (option 0-16MB I-TCM/D-TCM) |
Yes (option 0-16MB I-TCM/D-TCM) |
| TrustZone for Armv8-M |
No | No | No | Yes (option) | No | No | Yes (option) | Yes (option) | Yes (option) |
No |
| Coprocessor Interface | No | No | No | No | No | No | Yes (option) | Yes (option) | Yes (option) |
No |
| Bus Protocol |
AHB Lite | AHB Lite, Fast I/O | AHB Lite | AHB5, Fast I/O | AHB Lite, APB | AHB Lite, APB | AHB5, APB | AHB5, APB | AXI5 (main bus), AHB (peripheral bus, TCM slave port and debug) |
AXI4, AHB Lite, APB, TCM |
| Wake-up Interrupt Controller Support |
Yes | Yes | No | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Integrated Interrupt Controller (NVIC) |
Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Maximum # External Interrupts |
32 | 32 | 32 | 240 | 240 | 240 | 480 | 480 | 480 |
240 |
| Hardware Divide | No | No | No | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Single Cycle Multiply |
Yes (option) | Yes (option) | No | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| CMSIS Support |
Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Dual Core Lock-Step Support |
No | No | No | Yes | No | No | Yes | Yes | No |
Yes |
| Arm Custom Instructions |
No |
No |
No |
No |
No |
No |
Yes |
No |
Yes (available in 2021) |
No |
| Common Criteria certification | No | No | No | No | No | No | Yes | Yes | No | No |
*See individual Cortex-M product pages for further information.
SP = Single Precision
DP = Double Precision
HP = Half Precision
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