The Arm Cortex-M55 processor is Arm’s most AI-capable Cortex-M processor and the first to feature Arm Helium vector processing technology. It brings energy-efficient digital signal processing (DSP) and machine learning (ML) capabilities to the Cortex-M family. With the Cortex-M55 processor, developers can take advantage of the ease-of-use of Cortex-M, a single toolchain, optimized software libraries, and an industry-leading embedded ecosystem. The processor allows the integration of differentiating AI techniques, while staying within the system cost and energy constraints of battery powered IoT devices.

Architecture Armv8.1-M
Bus interface AMBA 5 AXI5 64-bit master (compatible to AXI4 IPs)
Pipeline 4-stage (for main integer pipeline)
Security Arm TrustZone technology (optional)
DSP extension
32-bit DSP/SIMD extension
M-Profile Vector Extension (MVE) Helium (optional)
Floating-point Unit (FPU)
Coprocessor interface   
64-bit (optional)
Instruction cache
Up to 64KB with ECC (optional)
Data cache
Up to 64KB with ECC (optional)
Instruction TCM (ITCM)
Up to 16MB with ECC (optional)
Up to 16MB with ECC (optional)
Up to 480 interrupts + Non-maskable interrupt (NMI)
Wake-up Interrupt Controller (WIC) Internal and/or external (optional)
Multiply-accumulate (MAC) / cycle
Up to:
2 x 32-bit MACs/cycle
4 x 16-bit MACs/cycle
8 x 8-bit MACs/cycle
Sleep modes
Multiple power domains
Sleep modes (sleep and deep sleep)
Optional retention support for memories and logic
Hardware and software breakpoints
Performance Monitoring Unit (PMU)
Trace Optional Instruction trace with Embedded Trace Macrocell (ETM), Data Trace (DWT) (selective data trace), and Instrumentation Trace (ITM) (software trace)
Arm Custom Instructions
Optional (available in 2021)
ECC on instruction cache, data cache, instruction TCM, data TCM (optional)
Bus interface protection (optional)
PMC-100 (Programmable MBIST Controller, optional)
Reliability, availability and serviceability (RAS) extension
Reference package or system example Corstone-300


Performance efficiency 4.2 CoreMark/MHz* and 1.6 DMIPS/MHz*.

*Please contact Arm for compilation conditions, as well as implementation data.