Cortex-M7

The Arm Cortex-M7 processor is the highest performance member of the energy-efficient Cortex-M processor family.

Block Diagram on Cortex-7.

Getting Started

The Cortex-M7 enables partners to build the most sophisticated variety of MCUs and embedded SoCs. It has been designed to deliver a very high level of performance, while maintaining the excellent responsiveness and ease-of-use of the Armv7-M architecture. Its industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas including automotive, industrial automation, medical devices, high-end audio, image and voice processing, sensor fusion and motor control.


Specifications

Architecture Armv7E-M
ISA Support Thumb/Thumb2
Pipeline 6-stage superscalar + branch prediction
DSP Extension
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide
Floating-Point Unit
Optional single and double precision floating point unit (choices of none, single precision only, and single and double precision)
IEEE 754 compliant
Interconnect
64-bit AMBA4 AXI, 32-bit AHB peripheral port
32-bit AHB slave port for external master (e.g. DMA controller) to access TCMs
APB interface for CoreSight debug components
Instruction cache
0 to 64 KB, 2-way associative with optional ECC
Data cache
0 to 64 KB, 4-way associative with optional ECC
Instruction TCM
0 to 16 MB with optional ECC interface
Data TCM
0 to 16 MB with optional ECC interface
Memory Protection
Optional 8 or 16 region MPU with sub regions and background region
Bit Manipulation
Integrated Bit-Field Processing Instructions
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels
8 to 256 priority levels
Wake-up Interrupt Controller
Optional
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM). Optional full data trace with ETM
Dual Core Lock-Step Support (DCLS)
Yes, DCLS configuration

Compare all Cortex-M processors

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Characteristics

Performance Efficiency: 5.01 CoreMark/MHz* and 2.14/3.23 DMIPS/MHz**

Arm Cortex-M7 implementation data*** 
   
  40LP
(9-track, typical 0.99v, 40°C)
 28HT
(9-track, typical 0.81v, 85°C)
16FFC
(7-track, typical 0.72v, 85°C) 
Dynamic Power
 58.5 µW/MHz
31.8 µW/MHz 18.5 µW/MHz
Floor Planned Area
 0.105 mm2 0.052 mm2   0.028 mm2

* See product, compiler and compiler flags

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits simultaneous ("multi-file") compilation. Both are with the original (K&R) v2.1 of Dhrystone

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug


  • Manual containing technical information.
  • Cortex-M7 Technical Reference Manual

    For system designers, system integrators, verification engineers and software programmers who are building a Cortex-M7 based SoC.


    Read here
  • A program that is running on a desktop.
  • Cortex-M7 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex‐M7 processor.

    Read here
  • A line drawing of a book.
  • Armv7-M Architecture Reference Manual

    This manual describes the instruction set, memory model, and programmers' model for Armv7-M compliant processors.

    Read here
  • Board that is the international standard.
  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • Systems supporting the main system.
  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here
  • A guide on software optimization.
  • DSP Extension

    DSP extension to the Thumb instruction set improves the performance of numerical algorithms. They provide the opportunity to perform signal processing operations directly on the Cortex-M7.

    Read here
  • Manual containing technical information.
  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors.

    Read here

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU Regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M7 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
Tools
Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK Software Development Tool

Arm Cortex-M7 Software Development Support

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Answered hardfault error
  • Cortex-M4
0 votes 925 views 4 replies Latest 3 days ago by 42Bastian Schick Answer this
Suggested answer Can I run an A9 program under A53 without any modification 0 votes 840 views 1 replies Latest 3 days ago by 42Bastian Schick Answer this
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) 0 votes 245 views 2 replies Latest 4 days ago by qinwenjian Answer this
Answered MPS2+ Expansion ports possible frequency and usage
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  • FPGA
  • iOS
  • Cortex-M
  • Cortex-M Prototyping System (V2M-MPS2)
0 votes 3514 views 6 replies Latest 4 days ago by kfzhang Answer this
Not answered There was a problem compiling the content above design start eval. 1 votes 81 views 0 replies Started 5 days ago by qinwenjian Answer this
Suggested answer Reading ETB from software
  • CoreSight ETB11
  • Cortex-A9
0 votes 2380 views 1 replies Latest 10 days ago by 42Bastian Schick Answer this
Answered hardfault error Latest 3 days ago by 42Bastian Schick 4 replies 925 views
Suggested answer Can I run an A9 program under A53 without any modification Latest 3 days ago by 42Bastian Schick 1 replies 840 views
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) Latest 4 days ago by qinwenjian 2 replies 245 views
Answered MPS2+ Expansion ports possible frequency and usage Latest 4 days ago by kfzhang 6 replies 3514 views
Not answered There was a problem compiling the content above design start eval. Started 5 days ago by qinwenjian 0 replies 81 views
Suggested answer Reading ETB from software Latest 10 days ago by 42Bastian Schick 1 replies 2380 views