Specifications
The Arm Cortex-M7 processor is the highest performance member of the energy-efficient Cortex-M processor family.
The Cortex-M7 enables partners to build the most sophisticated variety of MCUs and embedded SoCs. It has been designed to deliver a very high level of performance, while maintaining the excellent responsiveness and ease-of-use of the Armv7-M architecture. Its industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas including automotive, industrial automation, medical devices, high-end audio, image and voice processing, sensor fusion and motor control.
Arm Cortex-M7 processor
| Architecture | Armv7E-M |
| ISA Support | Thumb/Thumb2 |
| Pipeline | 6-stage superscalar + branch prediction |
| DSP Extension |
Single cycle 16/32-bit MAC Single cycle dual 16-bit MAC 8/16-bit SIMD arithmetic Hardware Divide |
| Floating-Point Unit |
Optional single and double precision floating point unit (choices of none, single precision only, and single and double precision) IEEE 754 compliant |
| Bus Interface |
64-bit AMBA4 AXI, 32-bit AHB peripheral port 32-bit AMBA AHB slave port for external master (e.g. DMA controller) to access TCMs AMBA APB interface for CoreSight debug components |
| Instruction cache |
0 to 64 KB, 2-way associative with optional ECC |
| Data cache |
0 to 64 KB, 4-way associative with optional ECC |
| Instruction TCM |
0 to 16 MB with optional ECC interface |
| Data TCM |
0 to 16 MB with optional ECC interface |
| Memory Protection |
Optional 8 or 16 region MPU with sub regions and background region |
| Bit Manipulation |
Integrated Bit-Field Processing Instructions |
| Interrupts | Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts |
| Interrupt Priority Levels |
8 to 256 priority levels |
| Wake-up Interrupt Controller |
Optional |
| Sleep Modes |
Integrated WFI and WFE Instructions and Sleep On Exit capability Sleep & Deep Sleep Signals. Optional Retention Mode with Arm Power Management Kit |
| Debug |
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints |
| Trace | Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM). Optional full data trace with ETM |
| Dual Core Lock-Step Support (DCLS) |
Yes, DCLS configuration |
Compare the specifications of Cortex-M processors:
Download comparison table
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.
Characteristics
Performance Efficiency: 5.01 CoreMark/MHz* and 2.14/3.23 DMIPS/MHz**
| Arm Cortex-M7 implementation data*** |
|||
| 40LP (9-track, typical 0.99v, 40°C) |
28HT (9-track, typical 0.81v, 85°C) |
16FFC (7-track, typical 0.72v, 85°C) |
|
| Dynamic Power |
58.5 µW/MHz |
31.8 µW/MHz | 18.5 µW/MHz |
| Floor Planned Area |
0.105 mm2 | 0.052 mm2 | 0.028 mm2 |
* See product, compiler and compiler flags
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits simultaneous ("multi-file") compilation. Both are with the original (K&R) v2.1 of Dhrystone
*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug