Cortex-M7

The Arm Cortex-M7 processor is the highest performance member of the energy-efficient Cortex-M processor family.

Block Diagram on Cortex-7.

Getting Started

The Cortex-M7 enables partners to build the most sophisticated variety of MCUs and embedded SoCs. It has been designed to deliver a very high level of performance, while maintaining the excellent responsiveness and ease-of-use of the Armv7-M architecture. Its industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas including automotive, industrial automation, medical devices, high-end audio, image and voice processing, sensor fusion and motor control.

Specifications

Architecture Armv7E-M
ISA Support Thumb/Thumb2
Pipeline 6-stage superscalar + branch prediction
DSP Extension
 Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide
Floating-Point Unit
 Optional single and double precision floating point unit (choices of none, single precision only, and single and double precision)
IEEE 754 compliant
Bus Interface 64-bit AMBA4 AXI, 32-bit AHB peripheral port
32-bit AMBA AHB slave port for external master (e.g. DMA controller) to access TCMs
AMBA APB interface for CoreSight debug components
Instruction cache
 0 to 64 KB, 2-way associative with optional ECC
Data cache
 0 to 64 KB, 4-way associative with optional ECC
Instruction TCM
 0 to 16 MB with optional ECC interface
Data TCM
 0 to 16 MB with optional ECC interface
Memory Protection
 Optional 8 or 16 region MPU with sub regions and background region
Bit Manipulation
 Integrated Bit-Field Processing Instructions
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels
 8 to 256 priority levels
Wake-up Interrupt Controller
 Optional
Sleep Modes
 Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Debug
 Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM). Optional full data trace with ETM
Dual Core Lock-Step Support (DCLS)
 Yes, DCLS configuration

Compare all Cortex-M processors

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Characteristics

Performance Efficiency: 5.01 CoreMark/MHz* and 2.14/3.23 DMIPS/MHz**

Arm Cortex-M7 implementation data*** 
    
  40LP
(9-track, typical 0.99v, 40°C)
  28HT
(9-track, typical 0.81v, 85°C)		 16FFC
(7-track, typical 0.72v, 85°C) 
Dynamic Power
  58.5 µW/MHz
 31.8 µW/MHz 18.5 µW/MHz
Floor Planned Area
  0.105 mm2 0.052 mm2   0.028 mm2

* See product, compiler and compiler flags

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits simultaneous ("multi-file") compilation. Both are with the original (K&R) v2.1 of Dhrystone

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug

Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
 Armv6-M
 Armv8-M Baseline 
 Armv7-M Armv7-M
 Armv8-M Mainline
 Armv8-M Mainline
 Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb, Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
 Thumb,
Thumb-2
DMIPS/MHz range*
 0.87-1.27  0.95-1.36  0.8
 0.98 1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
 2.33 2.46  1.85
 2.64 3.34 3.42  4.02 4.02 5.01
Pipeline Stages
 3  2  3  2  3  3  3  3  6 
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 		 Yes (option)  Yes (option)  Yes (option)
(2 x) 		 Yes (option)
(2 x) 		 Yes (option) 
Maximum MPU Regions  0  8  0  16  8  8  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 		 ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 		 MTB (option) and/or
ETMv4 (option)  		ETMv4 (option)
Digital Signal Processing (DSP) No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating Point Hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
 Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
 No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus Protocol
 AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
 Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated Interrupt Controller (NVIC)
 Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # External Interrupts
 32  32  32  240  240  240  480 480 240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single Cycle Multiply
 Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
 Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
 No No No Yes  No No Yes Yes  Yes 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

Related IP

The Cortex-M7 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
 Tools
 Software

Corstone Foundation IP

Socrates System Builder

Direct Memory Access Controller

Arm Development Studio

Arm Keil MDK Software Development Tool

Arm Cortex-M7 Software Development Support

Cortex-M Prototyping System

Fast Models

Cortex Microcontroller Software Interface Standard

Pelion IoT Platform

Mbed OS

Software Test Libraries

Trusted Firmware-M

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

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11 months ago by Chris Shore
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Arm’s face verification system is a real-time proof of concept that achieves 98.36% accuracy, running efficiently on Arm machine learning-optimized platforms.

1 years ago by Konstantinos Monachopoulos
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Tutorial: Low Power Deep Learning on the OpenMV Cam

Check out OpenMV's latest tutorial to learn how to run deep learning on the Arm Cortex-M7 processor using CMSIS-NN with the OpenMVCam.

1 years ago by Louise Paul
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Community Forums

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Suggested answer How to access memory more than 4GB by using 32bit ISA? Latest 8 hours ago by Martin Weidmann 5 replies 567 views
Suggested answer Saving processor state for power-down and resume Latest 12 hours ago by 42Bastian Schick 1 replies 93 views
Suggested answer adc read Latest 13 hours ago by 42Bastian Schick 1 replies 104 views
Not answered How to write values ​​from secure code to non-secure memory. Started yesterday by Lars 0 replies 132 views
Not answered Cache Coherence Support in CHI Specification Started 2 days ago by JO16 0 replies 191 views
Not answered Pros and cons of activating cache in stm32F7 Started 2 days ago by Marzi 0 replies 165 views