Cortex-M7

The Arm Cortex-M7 processor is the highest performance member of the energy-efficient Cortex-M processor family.

Block Diagram on Cortex-7.

Getting Started

The Cortex-M7 enables partners to build the most sophisticated variety of MCUs and embedded SoCs. It has been designed to deliver a very high level of performance, while maintaining the excellent responsiveness and ease-of-use of the Armv7-M architecture. Its industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas including automotive, industrial automation, medical devices, high-end audio, image and voice processing, sensor fusion, advanced motor control and in the deployment of the Internet of Things (IoT).


Specifications

Architecture Harvard
ISA Support Armv7-M
Pipeline 6-stage superscalar + branch prediction
DSP Extensions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
Optional single and double precision floating point unit
IEEE 754 compliant
Interconnect
64-bit AMBA4 AXI, AHB peripheral port
Instruction cache
0 to 64 kB, 2-way associative with optional ECC
Data cache
0 to 64 kB, 4-way associative with optional ECC
Instruction TCM
0 to 16 MB with optional ECC
Data TCM
0 to 16 MB with optional ECC
Memory Protection
Optional 8 or 16 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels
8 to 256 priority levels
Wake-up Interrupt Controller
Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Debug
Integrated Instructions
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Trace

Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)

Compare all Cortex-M processors

Characteristics

Performance Efficiency: 5 CoreMark/MHz* and 2.14 / 2.55 / 3.23 DMIPS/MHz**

Arm Cortex-M7 implementation data*** 
  28 HPM
(9-track, typical 0.9v, 85°C)
Dynamic Power
 33 µW/MHz
Floorplan Area
 0.067mm2

* CoreMark 1.0 : IAR Embedded Workbench v7.30.1 --endian=little --cpu=Cortex-M7 -e -Ohs --use_c++_inline --no_size_constraints / Code in TCM - Data in TCM.

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

*** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU, FPU and debug.

 


  • Manual containing technical information.
  • Cortex-M7 Technical Reference Manual

    The complete reference manual for system development, verification and programming on Cortex-M7 based SoCs.

    Download
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • A guide on software optimization.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Cortex-M Comparison Table

Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M7 
Instruction set architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.99  1.25-1.89  1.25-1.95  1.5  1.5  2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.5 3.34 3.42  4.02 4.02 5.01
Pipeline stages
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) 
Maximum MPU regions  16  16  16  16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
DSP  No  No  No  No  No Yes  Yes (option) Yes (option)  Yes 
Floating point hardware  No No  No  No  No Yes (option SP) Yes (option SP)  Yes (option SP)  Yes
(option SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option 4-64kB 
 I-cache I-cache, D -cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  No 
Co-processor interface  No  No  No  No  No  No  Yes (option)  Yes (option)  No 
Bus protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5  AHB5 AXI4, AHB Lite, APB, TCM
Wake-up interrupt controller support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes 
Integrated interrupt controller
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes 
Maximum # external interrupts
32  32  32  240  240  240  480 480 240  
Hardware divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes 
Single cycle multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 
Dual Core Lock-Step Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes 

 *See individual Cortex-M product pages for further information.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-M7 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

 

Compatible IP
Tools
Software

Cortex-M System Design Kit

Socrates System Builder

AMBA System Controllers

DS-5 Development Studio

Arm Keil MDK software development tool

Arm Cortex-M7 Software Development Support

Cortex-M Prototyping System

Cortex Microcontroller Software Interface Standard

Arm Mbed Pelion Device Management

 

Community Blogs

Community Forums

Suggested answer Relocating the Vector table in Cortex - M0 0 votes 111 views 3 replies Latest 6 hours ago by Prasad Kadam Answer this
Suggested answer What options do I have for a GUI and an LCD? 0 votes 68 views 1 replies Latest 8 hours ago by Joseph Yiu Answer this
Discussion 4-kbyte boundary space 0 votes 9743 views 10 replies Latest 22 hours ago by Colin Campbell Answer this
Suggested answer Timer0 do not count at the theoretical frequency 0 votes 68 views 1 replies Latest 23 hours ago by 42Bastian Schick Answer this
Answered Disable data prefetching in a Cortex-A53 running Android
  • Cortex-A53
  • el1
  • l1
  • l2
0 votes 195 views 3 replies Latest yesterday by vstehle Answer this
Suggested answer Cortex M1 only runs in debugger (using ARTIX-7) 0 votes 265 views 3 replies Latest yesterday by Joseph Yiu Answer this
Suggested answer Relocating the Vector table in Cortex - M0 Latest 6 hours ago by Prasad Kadam 3 replies 111 views
Suggested answer What options do I have for a GUI and an LCD? Latest 8 hours ago by Joseph Yiu 1 replies 68 views
Discussion 4-kbyte boundary space Latest 22 hours ago by Colin Campbell 10 replies 9743 views
Suggested answer Timer0 do not count at the theoretical frequency Latest 23 hours ago by 42Bastian Schick 1 replies 68 views
Answered Disable data prefetching in a Cortex-A53 running Android Latest yesterday by vstehle 3 replies 195 views
Suggested answer Cortex M1 only runs in debugger (using ARTIX-7) Latest yesterday by Joseph Yiu 3 replies 265 views