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regions configured in the TZC-400 and the source from where the AXI-low power signals are coming to TZC-400
Where does the 9 regions supported by the TZC-400 are present and the source from where the AXI-low power signals are connected to TZC-400
L2 Cache ECC Notification
I am trying to implement L2 ECC for A72 core and its notification. What I have understood, L2 ECC can be enabled using L2CTLR_EL1 register. And L2 ECC system generates two error signals nEXTERRIRQ and nINTERRIRQ, I assume , nINTERRIRQ will be generated in case of double bit error. Could you help me, if there is some notification for single bit correctable error, which is done by L2 ECC block or say, in case some single bit correction done, How CPU will know
Generic Interrupt Controller Usage
Hi, I am trying to set up an interrupt mechanism on Agilex-7 Soc Dev Kit DK-DEV-AGF014EA. I enabled the Received Data Available interrupt on uart0 peripheral but I don't understand how to catch it and register the IRO to an ISR. The uart0_IRQ's GIC interrupt number is 140. Could you please help me about that? Best Regards, Balerion
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