- When will the Cortex-R5 processor abandon normal memory accesses on receiving an interrupt?
- >Clarification of the PARTNO value in the IDCODE and DPIDR registers of the DAP Debug Port
- ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
- How to pause system level timers while CPU execution is halted
- Design Sign-off Model (DSM) does not function correctly in simulation.
- Arm Cortex-R4 and Cortex-R4F Software Developers Errata Notice
- Cortex-R4 Cycle Model User Guide
- Core Tile for ARM Cortex-R4F User Guide
- Coding for the Cortex-R4(F) Whitepaper
- Cortex-R4 and Cortex-R4F Technical Reference Manual
- Managing Memory Protection Performance Concerns in Cached CortexTM R4/R5 Processors Application note 296
For additional information search for Cortex-R4.