Cortex-R7

The Cortex-R7 processor features an upgraded 11-stage, superscalar, out-of-order pipeline with advanced dynamic and static branch prediction, dynamic register re-naming and non-blocking Load-Store Unit. 

Cortex-R7 Block Diagram.

Getting Started

For the first time, there is also an integrated Generic Interrupt Controller (GIC), Snoop Control Unit (SCU) and timers to further reduce latency and enable symmetric multiprocessing in a dual core configuration.


Specifications

Architecture Armv7-R
Instruction Set Arm and Thumb-2. Supports DSP instructions and optional Floating-Point Unit with single-precision or double precision.
Microarchitecture 11-stage pipeline with instruction pre-fetch, branch prediction, superscalar and out of order execution, register renaming, parallel execution paths for load-store, MAC, shift-ALU, divide and floating-point. Also features a hardware divider and is binary compatible with the Arm9Arm11Cortex-R4 and Cortex-R5 embedded processors.
Cache controllers Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes configurable from 4 to 64KB. Cache lines are write-through.

Tightly-Coupled Memories Optional Tightly-Coupled Memory interfaces are for highly deterministic or low-latency applications that may not respond well to caching (e.g. instruction code for interrupt service routines and data that requires intense processing). Instruction and/or data TCMs. TCM size can be up to 128KB.
Interrupt Interface Standard interrupt, IRQ, non-maskable fast interrupt, FIQ, inputs are provided together with a fully integrated Generic Interrupt Controller (GIC) supporting complex priority-based interrupt handling. The processor includes low-latency interrupt technology that allows long multi-cycle instructions to be interrupted and restarted. Deferral of lengthy memory accesses occurs in certain circumstances.
Memory Protection Unit (MPU) Optional MPU configures attributes for up to sixteen regions, each with resolution down to 256 Bytes. Regions can overlap, and the highest numbered region has highest priority.

Floating-Point Unit (FPU) Optional FPU implements the Arm Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE754. There is support for two FPU options: either a single precision-only or both single and double precision. The FPU performance is optimized for both single and double precision calculations. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
ECC Optional single-bit error correction and two-bit error detection for cache and/or TCM memories and all interfaces with ECC bits. Single-bit soft errors are automatically corrected by the processor. In addition, full and flexible support for managing hard errors.
Master AMBA AXI bus 64-bit AMBA AXI bus master for Level-2 memory and peripheral access.
Slave AXI bus Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the TCMs for high speed streaming of data in and out of the processor.
Low Latency Peripheral Port (LLPP) A dedicated 32-bit AMBA AXI port to integrate latency-sensitive peripherals more tightly with the processor.
Accelerator Coherency Port (ACP) A 64-bit AMBA AXI slave port to enable coherency between the processor(s) and external intelligent peripherals such as DMA controllers, Ethernet or Flexray interfaces.
Low latency memory port A 64-bit AMBA AXI master port designed specifically to connect to local memory. This local memory provides many of the benefits of TCM and in addition can be slower and lower power and also easily shared between coherent peripherals and the one or two Cortex-R7 processor cores.
Dual-core A dual processor configuration for either a redundant Cortex-R7 CPU in lock-step for fault tolerant/fault detecting dependable systems or dual cores running independently, each executing its own program with its own bus interfaces, interrupts etc.
Debug Debug Access Port is provided. Its functionality can be extended using CoreSight SoC-400.
Trace An interface suitable for connection to CoreSight Embedded Trace Module is present.

Compare all Cortex-R processors

Characteristics

Processor area, frequency and power consumption are highly dependent on process, libraries and optimizations. The table below estimates a typical single processor implementation of the Cortex-R7 processor on mainstream high performance for mobile process technology (28nm HPM) with high-density, standard-performance cell libraries and 32KB instruction cache and 32KB data cache.

Single processor systems 28 nm HPM
Maximum Clock frequency Above 1.5 GHz
Performance 2.50 / 2.90 / 3.77 DMIPS/MHz *
4.62 CoreMark/MHz**
Total area (Including Core+RAM+Routing) From 0.33 mm2
Efficiency From 46 DMIPS/mW

* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile compilation. All are with the original (K&R) v2.1 of Dhrystone.

** CFLAGS ="--endian=little --cpu=Cortex-R7 --fpu=None -Ohs --no_size_constraints"


  • Manual containing technical information.
  • Cortex-R7 Technical Reference Manual

    In-depth technical information on the Cortex-R7 for system designers, integrators, verification engineers and software engineers.

    Read here
  • A program that is running on a desktop.
  • Cortex-R Series Programmer's Guide

    For Software developers working in assembly language, this guide covers programming Cortex-R series devices.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-R Series

    DS-5 Development Studio and a range of 3rd party and open source tools support Cortex-R series software development.

    Learn more

Comparing Cortex-R Series Processors

Arm Cortex-R4 Arm Cortex-R5 Arm Cortex-R7 Arm Cortex-R8  Arm Cortex-R52
1.67 / 2.01 / 2.45 DMIPS/MHz*
3.47 CoreMark/MHz**
1.67 / 2.01 / 2.45 DMIPS/MHz*
3.47 CoreMark/MHz***
2.50 / 2.90 / 3.77 DMIPS/MHz*
4.35 CoreMark/MHz****
2.50 / 2.90 / 3.77 DMIPS/MHz*
4.62 CoreMark/MHz****
2.04 / 2.6 / 5.07 DMIPS/MHz*
4.2 CoreMarks/MHz
Lockstep configuration Lockstep configuration
Dual-core Asymmetric Multi-Processing (AMP) configuration
Lockstep configuration
Dual-core Asymmetric Multi-Processing (AMP) with QoS configuration
Dual core Symmetric Multi-Processing (SMP) configuration
Lockstep configuration 
Dual, triple or quad-core Asymmetric Multi-Processing (AMP) with QoS configuration
Dual, triple or quad-core Symmetric Multi-Processing (SMP) configuration
Lockstep configuration 
Dual, triple or quad-core Asymmetric Multi-Processing (AMP) with QoS configuration
Dual, triple or quad-core Symmetric Multi-Processing (SMP) configuration

Tightly Coupled Memory (TCM) Tightly Coupled Memory
Low Latency Peripheral Port 
Accelerator Coherency Port
Micro Snoop Control Unit (µSCU)
Tightly Coupled Memory
Low Latency Peripheral Port 
Accelerator Coherency Port
Snoop Control Unit (SCU)
Tightly Coupled Memory
Low Latency Peripheral Port
Accelerator Coherency Port
Snoop Control Unit (SCU)

Tightly Coupled Memory
Low Latency Peripheral Port
Flash Port
8-stage dual issue pipeline with instruction pre-fetch and branch prediction 8-stage dual issue pipeline with instruction pre-fetch and branch prediction 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer
8-stage dual issue pipeline with instruction pre-fetch and branch prediction
I-Cache and D-Cache I-Cache and D-Cache I-Cache and D-Cache  I-Cache and D-Cache
I-Cache and D-Cache
Hardware divide, SIMD, DSP Hardware divide, SIMD, DSP Hardware divide, SIMD, DSP  Hardware divide, SIMD, DSP
Hardware divide, NEON
IEEE754 Double Precision FPU IEEE754 Double Precision FPU or optimized SP Floating Point Unit IEEE754 Double Precision FPU or optimized SP Floating Point Unit IEEE754 Double Precision FPU or optimized SP Floating Point Unit
IEEE754 Double Precision FPU or optimized SP Floating Point Unit
Memory Protection Unit (MPU) with 8 or 12 memory regions Memory Protection Unit (MPU) with 12 or 16 memory regions Memory Protection Unit (MPU) with 12 or 16 memory regions Memory Protection Unit (MPU) with 12, 16, 20 or 24 memory regions
Stage-1 Memory Protection Unit (MPU) with 0 or 16 memory regions
Stage-2 Memory Protection Unit (MPU) with 0 or 16 memory regions
ECC and Parity protection on L1 memories ECC and Parity protection on L1 memories and AXI bus ports ECC and Parity protection on L1 memories and AXI bus ports.
Error Management with error bank
ECC and Parity protection on L1 memories and AXI bus ports.
Error Management with error bank
ECC and Parity protection on L1 memories and AXI bus ports
Bus interconnect protection 
Vectored Interrupt Controller (VIC) Port or Generic Interrupt Controller (GIC) Vectored Interrupt Controller (VIC) or Generic Interrupt Controller (GIC) Integrated Generic Interrupt Controller (GIC) Integrated Generic Interrupt Controller (GIC)
Integrated Generic Interrupt Controller (GIC), 32-960 interrupts

* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile complilation. All are with the original (K&R) v2.1 of Dhrystone.

** CFLAGS ="--cpu cortex-r4 -O3 -Otime --fpu softvfp -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"

*** CFLAGS ="--cpu cortex-r5 -O3 -Otime --fpu softvfp -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"

**** CFLAGS ="--cpu cortex-r5f -O3 -Otime -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"

Cortex-R series processors are all binary compatible, enabling software reuse and a seamless progression from one Cortex-R processor to another as functionality and/or additional processing power is required.

11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer
Hardware divide, SIMD, DSP

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-R7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-R7 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP and tools include:

Compatible IP
Tools

CoreLink Network Interconnect Family

CoreLink Static Memory Controllers

Memory Controllers

Interrupt Controllers

Other System Controllers

CoreSight SoC-400

Logic IP

Embedded Memory IP

Trace Memory Controller

DS-5 Development Studio

Fast Models

Cycle Models

Development Boards

Community Blogs

Community Forums

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Suggested answer Can I run an A9 program under A53 without any modification Latest 23 hours ago by 42Bastian Schick 1 replies 750 views
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