The Cortex families
In 2004, Arm introduced the Cortex-M family with Cortex-M3. Cortex-M3 gave developers an energy-efficient MCU with a simpler programming model that does not require assembly coding.
Cortex-M3 features include automatic register stacking on interrupt entry, and a simple but low-latency vectored interrupt controller. Over time, the Cortex-M family expanded to add processors with additional features including Floating Point Unit (FPU), Single Instruction Multiple Data (SIMD), and most recently, TrustZone followed by vector processing.
When Cortex-M launched, there was already demand for a higher level of performance. Developers wanted a programmer’s model that was closer to Cortex-A, but suitable for markets with hard real-time requirements. Instead of a Memory Management Unit (MMU), Cortex-R processors were introduced with memory protection and tightly coupled memories. These features made it easier for Cortex-R processors to guarantee worst-case execution time and meet the needs of markets like storage, automotive, and modems. Other architectural optimizations include the ability to interrupt load/store multiple instructions. Interrupt controllers are often optimized for very low latency.
One of the biggest changes in recent years was the introduction of 64-bit processing to the Cortex-A family. This change was first incorporated in Cortex-A53 and Cortex-A57, in 2012. This development was in response to partner needs for the mobile phone market. Since then, the ecosystem has matured, and the market has grown to include HPC and hyperscale.
Cortex-R82 and the Armv8-R architecture
Cortex-R52, the first Armv8-R architecture processor, was announced in 2016. Cortex-R52 added an extra Exception level, EL2, to allow software to run a hard real-time hypervisor. Although virtualization is nothing new, the ability to execute virtualization without compromising real-time responsiveness is unique. This feature particularly benefits the automotive industry. Cortex-R82 continues with support for a Memory Protection Unit (MPU) at EL2, and MMU or MPU at EL1.
Cortex-R82 includes performance enhancements, and two major new features:
- 64-bit instruction set: For storage, 64-bit support provides the ability to address more than 4GB of memory. Modern SSDs need around 1GB of cache memory for every TB of disk capacity. This means that, as storage capacities continue to grow, the ability to support large cache memories is increasingly important. There is a second use case, too. Cortex-R82 can share the same address map and memory system as a 64-bit Cortex-A applications processor.
- MMU: The MMU gives Cortex-R82 the ability to run Linux. The processor still retains the classic Cortex-R features, including an MPU and Tightly Coupled Memories (TCMs). These features allow a cluster of cores to run a mix of hard real-time and rich OSs. This addresses new opportunities like computational storage.
The new features in Cortex-R82 provide access to the rich ecosystem of Linux and applications that are already ported to the Armv8-A architecture, but still provides the classic Cortex-R features of support for hard real time. Having an MMU might seem contradictory to this, given the risk of translation table walks at critical times. Cortex-R82 supports both MPU and MMU. Therefore, we might expect that hard real-time event handling is done with software using the MPU, which also gives access to TCMs, and that less critical code runs using the MMU. Translation table walks can be interrupted to switch to critical routines. Using TCMs for critical code and data guarantees that no walks are required by the handler routines themselves.
In many systems, we expect that, rather than operating multiple OSs on a single core, we will instead see multiple cores in a cluster with partitioning between dedicated real-time and Linux cores. This flexibility means that a single SoC can address multiple application use cases. This becomes more valuable as process geometries shrink and the cost of new tapeouts continues to rise.