Smallest footprint Machine Learning inference processor

Getting started

Optimized for the most cost and battery life sensitive designs, Ethos-N37 delivers premium AI experiences in entry phones and DTVs and other endpoint devices. With the highest performance, an open-source software framework and the largest AI ecosystem, the Arm AI platform makes it easy to develop on Arm.

Download the Ethos-N37 datasheet:

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Key features

High Efficiency

Delivers up to 1 TOP/s within 1mm2 using 512 8-Bit MACs.

Lowest Area

Smallest-area inference NPU brings battery life savings and quick integration for cost or thermally constrained designs.

Optimized Design

Drives up to 225% convolution performance uplift using Winograd on 3x3 kernels, delivering up to 90% MAC utilization.

Futureproof

Supports a wide range of existing Machine Learning (ML) operations and future innovations through firmware updates and compiler technology.

Arm Ethos-N Block Diagram

Ethos-N37 entry-level ML inference processor contains four compute engines

Key benefits

  • Supports a variety of popular neural networks, including CNNs and RNNs, for classification, object detection, image enhancements, speech recognition and natural language understanding
  • Reduces system memory bandwidth by 1.5-3x through clustering sparsity and workload tiling, with lossless compression for weights and activations on select networks
  • Maximizes the number of parameters stored on-chip by storing compressed weights and activations in local SRAM and decompressing them on the fly
  • Leverages sparse power gating techniques to reduce power by up to 50%
  • Improves performance and extends battery life through intelligent data management techniques to minimize memory movement with up to 90% of accesses on chip
  • Supports TrustZone system security to safeguard sensitive data with support for secure and non-secure modes.

Specifications

Key features Performance (at 1GHz)
1 TOP/s
MACs (8x8) 512
Data types Int-8 and Int-16
Network support CNN and RNN
Efficient convolution Winograd support
Sparsity Yes
Secure mode TEE or SEE
Multicore capability 8 NPUs in a cluster
64 NPUs in a mesh
Memory system Embedded SRAM 512 KB
Bandwidth reduction
Extended compression technology, layer/operator fusion
Main interface
1xAXI4 (128-bit), ACE-5 Lite
Development platform Neural frameworks TensorFlow, TensorFlow Lite, Caffe2, PyTorch, MXNet, ONNX
Neural operator API Arm NN, AndroidNN
Software components Arm NN, neural compiler, driver and support library
Debug and profile Layer-by-layer visibility
Evaluation and early prototyping Arm Juno FPGA systems and cycle models


Ethos-N comparison table

    Ethos-N77
Ethos-N57
Ethos-N37
Key features Performance (at 1GHz)
4 TOP/s 2 TOP/s 1 TOP/s
MAC/Cycle (8x8) 2048 1024
512
Data types
Int-8 and Int-16
Network support CNN and RNN
Efficient convolution
Winograd support
Sparsity Yes
Secure mode
TEE or SEE
Multicore capability 8 NPUs in a cluster
64 NPUs in a mesh
Memory system Embedded SRAM 1-4 MB 512 KB 512 KB
Bandwidth reduction Extended compression technology, layer/operator fusion, clustering, and workload tilling
Main interface 1xAXI4 (128-bit), ACE-5 Lite
Development platform Neural frameworks TensorFlow, TensorFlow Lite, Caffe2, PyTorch, MXNet, ONNX
  Neural operator API Arm NN, AndroidNN
  Software components Arm NN, neural compiler, driver and support library
  Debug and profile Layer-by-layer visibility
  Evaluation and early prototyping Arm Juno FPGA systems and cycle models

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Ethos-N37 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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Community Blogs

Community Forums

Answered hardfault error
  • Cortex-M4
0 votes 947 views 4 replies Latest 3 days ago by 42Bastian Schick Answer this
Answered MPS2+ Expansion ports possible frequency and usage
  • ANSI
  • FPGA
  • iOS
  • Cortex-M
  • Cortex-M Prototyping System (V2M-MPS2)
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Answered System Frequency for CortexA35
  • Cortex-A35
  • Armv8-A
0 votes 3253 views 1 replies Latest 18 days ago by vstehle Answer this
Answered mips of cortex a53 0 votes 5026 views 6 replies Latest 18 days ago by vstehle Answer this
Answered Address of core register on M0+ core 0 votes 849 views 2 replies Latest 20 days ago by M_T Answer this
Answered How vRestoreContextOfFirstTask works 0 votes 1099 views 3 replies Latest 21 days ago by Shibasis Answer this
Answered hardfault error Latest 3 days ago by 42Bastian Schick 4 replies 947 views
Answered MPS2+ Expansion ports possible frequency and usage Latest 4 days ago by kfzhang 6 replies 3528 views
Answered System Frequency for CortexA35 Latest 18 days ago by vstehle 1 replies 3253 views
Answered mips of cortex a53 Latest 18 days ago by vstehle 6 replies 5026 views
Answered Address of core register on M0+ core Latest 20 days ago by M_T 2 replies 849 views
Answered How vRestoreContextOfFirstTask works Latest 21 days ago by Shibasis 3 replies 1099 views