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Answered How long are the Cortex-M7 pipeline stages?
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0 votes 27837 views 18 replies Latest 2 days ago by Pacocha Answer this
Answered Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
  • AArch64
  • Armv8-A
  • AArch32
0 votes 970 views 2 replies Latest 3 days ago by George_ Answer this
Answered Disable Cache L1 et L2 Armv8
  • Cortex-A72
  • Cache
  • Armv8-A
1 votes 1567 views 7 replies Latest 6 days ago by 42Bastian Schick Answer this
Answered Is Advanced-SIMD supported in Cortex-R5F?
  • Cortex-R
  • Cortex-R5
  • Armv7-R
  • SIMD and Vector Execution
0 votes 4411 views 4 replies Latest 9 days ago by Koppu Answer this
Answered How long are the Cortex-M7 pipeline stages? Latest 2 days ago by Pacocha 18 replies 27837 views
Answered Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1? Latest 3 days ago by George_ 2 replies 970 views
Answered Disable Cache L1 et L2 Armv8 Latest 6 days ago by 42Bastian Schick 7 replies 1567 views
Answered Is Advanced-SIMD supported in Cortex-R5F? Latest 9 days ago by Koppu 4 replies 4411 views