Arm Machine Learning Processor 

Industry-leading performance and efficiency for inference at the edge.

Machine Learning Processor Block Diagram.

The Arm Machine Learning processor is an optimized, ground-up design for machine learning acceleration, targeting mobile and adjacent markets. The solution consists of state-of-the-art optimized fixed-function engines that provide best-in-class performance within a constrained power envelope.

Additional programmable layer engines support the execution of non-convolution layers, and the implementation of selected primitives and operators, along with future innovation and algorithm generation. The network control unit manages the overall execution and traversal of the network and the DMA moves data in and out of the main memory.

Onboard memory allows central storage for weights and feature maps, thus reducing traffic to the external memory and therefore, power.


Key Features

  • Specially designed to provide outstanding performance for mobile with up to 4 TOPs; additional optimizations provide a further increase in real-world use cases.
  • Best-in-class efficiency at >4 TOPs/W.
  • Programmable layer engines for future-proofing.
  • Highly tuned for advanced geometry implementations.
  • Scalable onboard memory reduces external memory traffic.
  • Arm NN works with Android NNAPI to provide a translation layer between major neural network frameworks, such as TensorFlow and Caffe, and the Arm Machine Learning processor, as well as other Arm IP.

Performance

  • Greater than 4 TOPs in mobile environments.
  • Propriety optimizations provide further increase in real-world use cases.
  • Efficiency of >4 TOPs/W.

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To learn more about Machine Learning on Arm, visit our ML Developer community.

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Key Benefits

  • Most efficient solution to run neural networks.
  • Designed for the mobile and adjacent markets.
  • Optimized, ground-up design for machine learning acceleration.
  • Best-in-class performance with state-of-the-art, fixed-function engines.
  • Programmable engines for future innovation and algorithms.
  • Massive efficiency uplift from CPUs, GPUs, DSPs and accelerators.
  • Completes Arm’s heterogeneous Machine Learning platform solution.
  • Enabled by open-source software.
  • Industry-leading performance in thermally- and cost-constrained environments.

Applications

Mobile

AR/VR

IoT

Smart camera

Healthcare

Medical

Logistics

Small area

Robotics

Home

Consumer 

Drones

Wearables

Webinar - Project Trillium: Optimizing ML Performance for any Application

Project Trillium is a suite of Arm IP designed to deliver scalable ML and neural network functionality at any point on the performance curve, from sensors, to mobile, and beyond. 

 

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Not answered Trigger a Software Interrupt 0 votes 13 views 0 replies Started 8 hours ago by Aquox Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
0 votes 108 views 3 replies Latest 12 hours ago by 42Bastian Schick Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 45 views 0 replies Started 2 days ago by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
0 votes 874 views 20 replies Latest 5 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 65 views 0 replies Started 5 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 69 views 0 replies Started 5 days ago by BAB Answer this
Not answered Trigger a Software Interrupt Started 8 hours ago by Aquox 0 replies 13 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 12 hours ago by 42Bastian Schick 3 replies 108 views
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 2 days ago by jing 0 replies 45 views
Answered Binary Semaphore upset by FIQ Latest 5 days ago by 42Bastian Schick 20 replies 874 views
Not answered Identifying Generic IP Components on an Access Port Started 5 days ago by Torsten Robitzki 0 replies 65 views
Not answered Issue with WatchDog reset De-asserting Started 5 days ago by BAB 0 replies 69 views