Neoverse E1

The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

Neoverse E1 block diagram

Getting started

The Arm Neoverse E1 CPU delivers best in class throughput efficiency. It incorporates a new simultaneous multithreading (SMT) microarchitecture design. With SMT, the processor can execute two threads concurrently resulting in better aggregate throughput performance.

The Neoverse E1 delivers 2.1x more compute performance, 2.7x more throughput performance and 2.4x better throughput efficiency compared to the Cortex-A53. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Specifications

General Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Advanced SIMD and floating-point
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product support instructions
  • Armv8.5 PSTATE SSBS bit
  ISA support A64
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon and Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
  Physical addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache and D-Cache 32KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Safety package
Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

Arm Security Algorithm Accelerators

Download the hardware block:

Neoverse-E1_Security_Algorithm_Accelerator.tar.gz 468 KB

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Answered ARM - Mali - G78 MP14 power consumption - 30fps 0 votes 279 views 3 replies Latest 18 hours ago by Peter Harris Answer this
Answered Virtual interrupt EOI mode & irq state
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Answered Issue with Performance Adviser pa command
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Answered Mali GPU Counters 0 votes 469 views 8 replies Latest yesterday by Peter Harris Answer this
Answered Cortex-M3 DA addressing not allowed for STM
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Answered Arm Compiler V6.15 LTO Optimizations and -Oz
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0 votes 194 views 1 replies Latest 2 days ago by Ronan Synnott Answer this
Answered ARM - Mali - G78 MP14 power consumption - 30fps Latest 18 hours ago by Peter Harris 3 replies 279 views
Answered Virtual interrupt EOI mode & irq state Latest 22 hours ago by George_ 2 replies 245 views
Answered Issue with Performance Adviser pa command Latest yesterday by Dmitry Artamonov 6 replies 336 views
Answered Mali GPU Counters Latest yesterday by Peter Harris 8 replies 469 views
Answered Cortex-M3 DA addressing not allowed for STM Latest 2 days ago by 42Bastian Schick 5 replies 306 views
Answered Arm Compiler V6.15 LTO Optimizations and -Oz Latest 2 days ago by Ronan Synnott 1 replies 194 views