Neoverse E1

The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

Neoverse E1 block diagram

Getting started

The Arm Neoverse E1 CPU delivers best in class throughput efficiency. It incorporates a new simultaneous multithreading (SMT) microarchitecture design. With SMT, the processor can execute two threads concurrently resulting in better aggregate throughput performance.

The Neoverse E1 delivers 2.1x more compute performance, 2.7x more throughput performance and 2.4x better throughput efficiency compared to the Cortex-A53. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Specifications

General Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Advanced SIMD and floating-point
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product support instructions
  • Armv8.5 PSTATE SSBS bit
  ISA support A64
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon and Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
  Physical addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache and D-Cache 32KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Safety package
Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

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Answered Where should I ask my question?
  • ARM Community
0 votes 8000 views 5 replies Latest 2 months ago by Andy Neil Answer this
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 129 views 2 replies Latest 17 hours ago by Tapas Answer this
Answered STM32 UART DMA can receive first time correct then it receive nothing 0 votes 4461 views 4 replies Latest 3 days ago by neo_hoang Answer this
Answered AXI4 - Data before address - why?
  • Address
  • AXI4
0 votes 313 views 6 replies Latest 4 days ago by af_23 Answer this
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 226 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Answered uVision 5.29.0.0 crashes when opening the debugger
  • Keil MDK
  • uVision
  • Debugger
0 votes 231 views 1 replies Latest 5 days ago by MTC Answer this
Answered Where should I ask my question? Latest 2 months ago by Andy Neil 5 replies 8000 views
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 17 hours ago by Tapas 2 replies 129 views
Answered STM32 UART DMA can receive first time correct then it receive nothing Latest 3 days ago by neo_hoang 4 replies 4461 views
Answered AXI4 - Data before address - why? Latest 4 days ago by af_23 6 replies 313 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 4 days ago by Colin Campbell 1 replies 226 views
Answered uVision 5.29.0.0 crashes when opening the debugger Latest 5 days ago by MTC 1 replies 231 views