Neoverse E1

The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

Neoverse E1 block diagram

Getting started

The Arm Neoverse E1 CPU delivers best in class throughput efficiency. It incorporates a new simultaneous multithreading (SMT) microarchitecture design. With SMT, the processor can execute two threads concurrently resulting in better aggregate throughput performance.

The Neoverse E1 delivers 2.1x more compute performance, 2.7x more throughput performance and 2.4x better throughput efficiency compared to the Cortex-A53. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Specifications

General Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Advanced SIMD and floating-point
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product support instructions
  • Armv8.5 PSTATE SSBS bit
  ISA support A64
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon and Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
  Physical addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache and D-Cache 32KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Safety package
Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

Get support

Community blogs

Community forums

Answered DS-5 5.29.0 on Windows 10 1803 0 votes 8731 views 6 replies Latest yesterday by Doyle2324 Answer this
Answered UART Baud rate CMSIS Drivers 0 votes 1489 views 6 replies Latest yesterday by Robert McNamara Answer this
Answered DSTREAM networking ports 0 votes 283 views 3 replies Latest 2 days ago by Stephen Theobald Answer this
Answered Address memory of the next instruction in A9 MPCore
  • R15 (PC Program Counter)
0 votes 784 views 3 replies Latest 3 days ago by dVaquerizo Answer this
Answered How to flush write buffer when memory attribute is normal_nc
  • Cache coherency
0 votes 860 views 4 replies Latest 3 days ago by bamvor_china Answer this
Answered DSTREAM network configuration from linux 0 votes 281 views 2 replies Latest 4 days ago by Joe Kulig Answer this
Answered DS-5 5.29.0 on Windows 10 1803 Latest yesterday by Doyle2324 6 replies 8731 views
Answered UART Baud rate CMSIS Drivers Latest yesterday by Robert McNamara 6 replies 1489 views
Answered DSTREAM networking ports Latest 2 days ago by Stephen Theobald 3 replies 283 views
Answered Address memory of the next instruction in A9 MPCore Latest 3 days ago by dVaquerizo 3 replies 784 views
Answered How to flush write buffer when memory attribute is normal_nc Latest 3 days ago by bamvor_china 4 replies 860 views
Answered DSTREAM network configuration from linux Latest 4 days ago by Joe Kulig 2 replies 281 views