Neoverse E1

The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

Neoverse E1 block diagram

Getting started

The Arm Neoverse E1 CPU delivers best-in-class throughput efficiency. It incorporates a new simultaneous multithreading (SMT) microarchitecture design. With SMT, the processor can execute two threads concurrently resulting in better aggregate throughput performance.

The Neoverse E1 delivers 2.1x more compute performance, 2.7x more throughput performance and 2.4x better throughput efficiency compared to the Cortex-A53. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Specifications

General Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Advanced SIMD and floating-point
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product support instructions
  • Armv8.5 PSTATE SSBS bit
  ISA support A64
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon/Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
  Physical addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache / D-Cache 32KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Safety package
Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

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Answered Where do I find presentations and photos from SC'18? 1 votes 892 views 0 replies Started 5 months ago by John Linford Answer this
Not answered Create standalone function to be loaded into Code memory 0 votes 11 views 0 replies Started 7 hours ago by RSB Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
0 votes 47 views 2 replies Latest 8 hours ago by Juanea7 Answer this
Answered Load an image in QVGA format into a ARM Compute Library ICTensor.
  • Arm Compute Library (ACL)
0 votes 420 views 1 replies Latest yesterday by Gian Marco Iodice Answer this
Suggested answer Code is not run after loading into chip 0 votes 67 views 1 replies Latest yesterday by Bojan Potocnik Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 35 views 0 replies Started 2 days ago by jing Answer this
Answered Where do I find presentations and photos from SC'18? Started 5 months ago by John Linford 0 replies 892 views
Not answered Create standalone function to be loaded into Code memory Started 7 hours ago by RSB 0 replies 11 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 8 hours ago by Juanea7 2 replies 47 views
Answered Load an image in QVGA format into a ARM Compute Library ICTensor. Latest yesterday by Gian Marco Iodice 1 replies 420 views
Suggested answer Code is not run after loading into chip Latest yesterday by Bojan Potocnik 1 replies 67 views
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 2 days ago by jing 0 replies 35 views