Neoverse E1

The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

Neoverse E1 block diagram

Getting started

The Arm Neoverse E1 CPU delivers best in class throughput efficiency. It incorporates a new simultaneous multithreading (SMT) microarchitecture design. With SMT, the processor can execute two threads concurrently resulting in better aggregate throughput performance.

The Neoverse E1 delivers 2.1x more compute performance, 2.7x more throughput performance and 2.4x better throughput efficiency compared to the Cortex-A53. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Specifications

General Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Advanced SIMD and floating-point
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product support instructions
  • Armv8.5 PSTATE SSBS bit
  ISA support A64
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon and Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
  Physical addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache and D-Cache 32KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Safety package
Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

Get support

Community blogs

Community forums

Discussion SAU vs. IDAU in a System with Multiple Masters
  • Security
  • TrustZone
  • Armv8-M
0 votes 9960 views 5 replies Latest 8 hours ago by Chris Reed Answer this
Answered 32-bit x 32-bit --->64-bit multiply
  • Cortex-M0
  • Cortex-M0+
  • Arm Assembly Language (ASM)
0 votes 531 views 4 replies Latest yesterday by Sean Dunlevy Answer this
Answered Program size of empty main function 0 votes 219 views 3 replies Latest yesterday by slawek krzysiek Answer this
Answered Does ARMv8.5 Branch Target Identification works for hugepages (2MiB) memory mapping? 0 votes 69 views 1 replies Latest yesterday by qwertytmp1 Answer this
Answered How to run arm code in x86 linux host machine? 0 votes 1448 views 2 replies Latest yesterday by Sajid Answer this
Answered How to enable a shared directory between the booted guest OS on Morello FVP and the host linux machine 0 votes 8097 views 11 replies Latest yesterday by Andy Nisbet Answer this
Discussion SAU vs. IDAU in a System with Multiple Masters Latest 8 hours ago by Chris Reed 5 replies 9960 views
Answered 32-bit x 32-bit --->64-bit multiply Latest yesterday by Sean Dunlevy 4 replies 531 views
Answered Program size of empty main function Latest yesterday by slawek krzysiek 3 replies 219 views
Answered Does ARMv8.5 Branch Target Identification works for hugepages (2MiB) memory mapping? Latest yesterday by qwertytmp1 1 replies 69 views
Answered How to run arm code in x86 linux host machine? Latest yesterday by Sajid 2 replies 1448 views
Answered How to enable a shared directory between the booted guest OS on Morello FVP and the host linux machine Latest yesterday by Andy Nisbet 11 replies 8097 views