Neoverse N1

Accelerating the transformation to a scalable cloud-to-edge infrastructure.

Neoverse N1 block diagram

Getting Started

The Arm Neoverse N1 CPU combines server-class features and thread performance with cutting -edge low power design techniques delivering revolutionary performance per watt for building the next-generation cloud-to-edge infrastructure. By co-optimizing the N1 CPU with the CMN-600 coherent mesh interconnect that supports chip-to-chip connectivity over CCIX, the N1 platform allows extreme scalability from 8 to16 cores/chip for networking, storage, security and edge compute nodes, to 128+ cores/socket in hyperscale servers. Built on a common Armv8.2-A software foundation with the Neoverse E1 CPU, seamless heterogeneous systems can be realized encompassing accelerated functions for infrastructure deployments in 5G, data analytics, and smart networking. Integrated with Arm’s ML processor, the N1 CPU can deliver a self-hosted inference accelerator for AI/ML applications.

Key Features

  • 30% more performance/watt than Cortex-A72 on the same technology node
  • Large 1MB private L2 cache with up to 128MB system level cache in the mesh interconnect
  • Low-latency direct-connect interface between the CPU and mesh interconnect
  • I-cache coherency to enable a broader range of server workloads
  • Microarchitecture for large footprint, branch-heavy workloads
  • Double the vector and crypto compute bandwidth over previous generation
  • Manageable, full-frequency, sustainable performance without compromising compute efficiency
  • Server-class virtualization, RAS and code profiling

Specifications

Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • SPE extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product instructions
  • Armv8.5 (security vulnerabilities mitigations)
ISA support
  • A64
  • A32 and T32 (at the EL0 only)
Microarchitecture Pipeline Out-of-order
Superscalar  Yes
Neon/Floating Point Unit  Included 
Cryptography Unit  Optional 
Max number of CPUs in cluster  Four (4) or direct-connect
Physical addressing (PA)  48-bit 
Memory system and external interfaces L1 I-Cache/D-Cache 64kB
L2 Cache 1MB to 512kB, or 256kB
L3 Cache  Optional, 512kB TO 4MB 
ECC Support  Yes 
LPAE  Yes
Bus interfaces  AMBA CHI or ACE
ACP  Optional with cluster
Peripheral Port Optional with cluster
Other Security  TrustZone
Interrupts  GIC interface, GICv34 
Generic timer  Armv8-A 
PMU  PMUv3
Debug  Armv8-A (plus Armv8.2-A extensions) 
CoreSight  CoreSightv3 
Embedded Trace Macrocell ETMv4.2 (instruction trace)

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Answered Where do I find presentations and photos from SC'18? 2 votes 1375 views 0 replies Started 9 months ago by John Linford Answer this
Suggested answer STM32F4 memcpy arry to structure other name addr hard-fault? 0 votes 129 views 3 replies Latest 5 hours ago by John Morris Answer this
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Suggested answer NVIC_EnableIRQ : enables only one interrupt at a time? 0 votes 117 views 4 replies Latest 6 hours ago by ArmAsking Answer this
Not answered Connecting Custom IP with ARM CortexM1 IP from DesignStart 0 votes 4 views 0 replies Started 7 hours ago by josina Answer this
Answered The boundary of stack 0 votes 138 views 4 replies Latest 11 hours ago by Oscar Huang Answer this
Answered Where do I find presentations and photos from SC'18? Started 9 months ago by John Linford 0 replies 1375 views
Suggested answer STM32F4 memcpy arry to structure other name addr hard-fault? Latest 5 hours ago by John Morris 3 replies 129 views
Not answered tech help support Started 6 hours ago by chris1522 0 replies 10 views
Suggested answer NVIC_EnableIRQ : enables only one interrupt at a time? Latest 6 hours ago by ArmAsking 4 replies 117 views
Not answered Connecting Custom IP with ARM CortexM1 IP from DesignStart Started 7 hours ago by josina 0 replies 4 views
Answered The boundary of stack Latest 11 hours ago by Oscar Huang 4 replies 138 views