Specifications

The Arm Neoverse N2 CPU builds on the leading performance per watt capabilities of Neoverse N1 by increasing scalar performance by 40%. Neoverse N2 is targeted at 5G, networking, SmartNICs, edge deployments, and hyperscale data centers. It allows partners to scale from low core-count edge systems to dense racks containing 128+ core cloud solutions.

Neoverse N2 is our first Armv9 infrastructure core, introducing new scalability, performance, and security features.

Neoverse N2 Diagram
Architecture Armv9.0-A (Harvard)
Extensions

Armv8.4

  • Scalable Vector Extensions
  • MPAM
  • Enhanced Nested Virtualization
  • Enhanced Cryptography
  • RAS Extensions
  • PMU Extensions

Armv8.4

  • Secure EL2
  • TLB Maintenance Ops
  • Small page tables
  • Flag Manipulation

Armv8.5

  • FP to Int
  • Enhanced Virtualization traps
  • BTI
  • Speculation control
  • Enhanced PMU

Armv8.6

  • Enhanced Pointer Authentication

Armv9

  • SVE2
  • Enhanced cryptography instructions
  • Embedded Trace Extension
  • Self-hosted Trace
ISA Support
  • A32 and T32 (at the EL0 only)
  • A64
Pipeline Out-of-order
Superscalar Yes
SVE2/Neon/Floating Point Unit 
Included
Cryptography Unit Optional
Max number of CPUs in cluster
Direct-connect
Physical Addressing (PA)
48-bit
L1 I-Cache/D-Cache
64kb
L2 Cache
1MB or 512kB
ECC Support
Yes
LPAE
Yes
Bus interfaces
AMBA CHI
Security TrustZone
Interrupts
GIC interface, GICv3 and GICv4
Generic timer 
Armv9-A 
PMU
PMUv3.4
Debug   Armv9-A (plus Armv8.2-A extensions)
CoreSight
CoreSightv3
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Key features

• 40% more scalar performance than Neoverse N1 at the same frequency.
• Maintains exceptional power and area efficiency of Neoverse N1.
• Scalable Vector Extension 2 (SVE2) builds on the foundations of SVE to bring the benefits of scalable SIMD vector performance and advanced auto-vectorization capabilities to a wider range of software.
• Memory Partitioning and Management (MPAM) to manage shared system resources based on software thread ID.
• Core scalability to 128-cores and beyond with Completer Busy (CBusy) aggressiveness back-off mechanism.
• Performance defined power (PDP) improves power efficiency by dynamically adjusting microarchitecture to match workload.
• Memory Tagging Extension (MTE) brings a performant and scalable hardware solution that reduces the exploitability of memory safety violations that might be present in code written in unsafe languages.
• Pointer authentication and branch target indicator help mitigate against return-oriented programming (ROP) and Jump-oriented programming (JOP) attacks.