Neoverse N2

This document describes the behavior of the different Performance Monitor Unit (PMU) events implemented in the Neoverse N2.

Background ... DBGBCR[ 8: 5] =='b1111 -> (BAS) Byte Address Select: for A64 and A32 instructions ... This means the updated breakpoint configuration might not take effect for many cycles.

Answer ... It is not efficient to enter retention when frequent wake-up events are expected. ... Examples: ... Since SystemReady compliance is not sought, SystemReady imposes no requirements.

Background ... Assumptions ... This means only one synchronizer is required for both inputs, and both processor ... This approach ... Enables correlation between CPU time and trace timestamps

Far atomics also cannot be performed speculatively, whereas the read prior to ... is coded. A far atomic operation using the STADD instruction would keep the cache line from being ... KBA

Technical Details ... Software Considerations ... However. ... Guidance for Software ... That patch enables the System Control Processor maintains a list (isolated_cpu_mpid_list) of ... KBA

Answer ... The CoreSight SoC-600 CTI does not natively provide a REQ/ACK interface, so a protocol ... Notes ... How do I drive a PMU snapshot interface using a CoreSight SoC-600 CTI? KBA

An IP bundle may require you to use an old version of Arm Compiler for validation. You may do so. ... Note ... Version(s) mentioned in processor IP bundle Actual version(s) 6.22.1

For Cortex-A/Cortex-AE/Cortex-X/Neoverse products, the AArch32/AArch64 support is ... *A510 r0 **A510 r1 ... 32/64 bit ARM Execution State support (Aarch32/AArch64) for ARM CPUs KBA

Enabling cycle and event counters ... If they are equal, this field has no effect on cycle count filtering in Non-secure ... The PMCCFILTR_EL0.RLK field controls cycle counting in Realm EL1.