Specifications

The Arm Neoverse V1 CPU ushers in a new performance tier to the Neoverse product portfolio. Targeted at HPC, HPC in the cloud and artificial intelligence and machine learning assisted workloads, it offers a 50% scalar and up to a 4X machine learning performance improvement over Neoverse N1. Neoverse V1 is the first Arm core to include Scalable Vector Extension support, providing 2x 256b SVE pipelines and twice the floating-point performance capability of Neoverse N1.

Built using latest features defined in Armv8-A architecture, V1 delivers higher performance per thread in a fully loaded system compared to traditional architectures.It is co-optimized with Neoverse CMN-650 and CMN-700 interconnects supporting high-bandwidth memory systems with DDR5 and HBM, and allowing for the on-die integration of specialized processors for matrix multiplication. Neoverse V1 introduces advanced power management capabilities with full flexibility to trade power versus performance, making it a versatile choice for deployment in both multi-user HPC cloud servers and extreme performance supercomputing applications. 

Neoverse V1 Diagram
Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1-8.4 Extensions without Secure-EL2
      • Scalable Vector Extensions (SVE)
      • Memory Partitioning and Monitoring (MPAM)
      • Enhanced Nested Virtualization
      • Cryptography Extensions including SM3/SM4
      • RAS Extensions
      • Activity Monitors
  • Armv8.5 Enhanced Statistical Profiling Extensions (SPE)
  • Armv8.5 (security vulnerabilities mitigations)
  • Armv8.5 Random Number Generator
  • Armv8.5 Cache Clean to Point of Deep Persistence
  • Armv8.5 Flag Manipulation
  • Armv8.6 bfloat/int8 matmul instructions
  • Armv8.6 Data Gather Hints (DGH)
  • Armv8.6 Pointer Authentication Enhancements
ISA Support
  • A32 and T32 (at the EL0 only)
  • A64
Pipeline Out-of-order
Superscalar Yes
SVE/Neon/Floating Point Unit 
Included
Cryptography Unit Included
Max number of CPUs in cluster
Direct-connect
Physical Addressing (PA)
48-bit
L1 I-Cache/D-Cache
64kb
L2 Cache
1MB or 512kB
ECC Support
Yes
LPAE
Yes
Bus interfaces
AMBA CHI
Security TrustZone
Interrupts
GIC interface, GICv34 
Generic timer 
Armv8-A 
PMU
PMUv3
Debug   Armv8-A (plus Armv8.2-A extensions)
CoreSight
CoreSightv3
Embedded Trace Macrocell ETMv4.2 (instruction trace)

Key features

  • 50% more scalar performance than Neoverse N1 at the same frequency
  • Scalable Vector Extension (SVE), a first for Neoverse, to support improved auto-vectorization and code longevity through vector length agnostic binaries:
    • Wider vector unit (2x256 bits),
    • Support for 2x2 matrix multiplication on bfloat16 and int8 data types.
  • Memory Partitioning and Management (MPAM) to manage shared system resources based on software thread ID
  • Completer Busy (CBusy) dynamic feedback mechanism to optimize traffic flow through the interconnect and memory subsystem
  • Supporting up to 96 outstanding memory transactions
  • Sophisticated power management