SecurCore

Arm SecurCore processors are designed specifically for high-performance and high-volume smartcard and embedded security applications. 

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Answered can we delay read and write transactions(axi4) by providing delay in register slice?
  • AXI4
0 votes 59642 views 67 replies Latest yesterday by casseverhart13 Answer this
Suggested answer MPU config and memory attributes
  • Cortex-M7
  • STM32
  • STM32 F7
0 votes 153 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer Old startup .s files from DS-1, etc. 0 votes 167 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer Transition from EL3 to EL1 on A53 0 votes 430 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer Cortex-A35 cache partitioning
  • Cache
  • Cache Management
  • Cache Architecture
0 votes 400 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer LPC2148 SoC 0 votes 968 views 5 replies Latest yesterday by Andy Neil Answer this
Answered can we delay read and write transactions(axi4) by providing delay in register slice? Latest yesterday by casseverhart13 67 replies 59642 views
Suggested answer MPU config and memory attributes Latest yesterday by 42Bastian Schick 1 replies 153 views
Suggested answer Old startup .s files from DS-1, etc. Latest yesterday by 42Bastian Schick 1 replies 167 views
Suggested answer Transition from EL3 to EL1 on A53 Latest yesterday by 42Bastian Schick 1 replies 430 views
Suggested answer Cortex-A35 cache partitioning Latest yesterday by 42Bastian Schick 1 replies 400 views
Suggested answer LPC2148 SoC Latest yesterday by Andy Neil 5 replies 968 views