SecurCore

Arm SecurCore processors are designed specifically for high-performance and high-volume smartcard and embedded security applications. 

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Not answered peripheral register access RMW vs Bit Banding 0 votes 33 views 0 replies Started 11 hours ago by Lorenz - ISRT GmbH Answer this
Not answered 2515 CAN controller with rpi3 0 votes 44 views 0 replies Started 16 hours ago by Tejadeep Answer this
Suggested answer Does "LDRD" instruction cause "UNDEFINSTR" error on Cortex-M4?
  • Cortex-M4
0 votes 608 views 6 replies Latest yesterday by Gavin Li Answer this
Answered What USB Blaster cable?
  • FPGA
  • USB
  • DesignStart
  • Cortex-M
  • Cortex-M Prototyping System (V2M-MPS2)
0 votes 4400 views 7 replies Latest yesterday by Javier4 Answer this
Not answered Arm DynamIQ Shared Unit
  • L3
  • DynamIQ
  • Cache Architecture
  • DSU
0 votes 78 views 0 replies Started 3 days ago by Errno Answer this
Not answered SDRAM Window Boundary in MPU Address space in Cyclone V (Dual Cortex A9)
  • Cortex-A9
0 votes 64 views 0 replies Started 3 days ago by Adeeljs Answer this
Not answered peripheral register access RMW vs Bit Banding Started 11 hours ago by Lorenz - ISRT GmbH 0 replies 33 views
Not answered 2515 CAN controller with rpi3 Started 16 hours ago by Tejadeep 0 replies 44 views
Suggested answer Does "LDRD" instruction cause "UNDEFINSTR" error on Cortex-M4? Latest yesterday by Gavin Li 6 replies 608 views
Answered What USB Blaster cable? Latest yesterday by Javier4 7 replies 4400 views
Not answered Arm DynamIQ Shared Unit Started 3 days ago by Errno 0 replies 78 views
Not answered SDRAM Window Boundary in MPU Address space in Cyclone V (Dual Cortex A9) Started 3 days ago by Adeeljs 0 replies 64 views