SecurCore

Arm SecurCore processors are designed specifically for high-performance and high-volume smartcard and embedded security applications. 

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Not answered Arm Musca A1 - SRAM0 MPC Security attribute during boot
  • Musca-A
  • TrustZone for Armv8-M
  • CoreLink SSE-200
0 votes 39 views 0 replies Started 13 hours ago by Daniel Oliveira Answer this
Suggested answer Cortex A-35 prevent fetch code allocation in cache 0 votes 200 views 2 replies Latest 13 hours ago by Etienne Alepins Answer this
Suggested answer Is it possible to move up from EL0 AARCH32 to EL1 AARCH64 0 votes 282 views 1 replies Latest 15 hours ago by vstehle Answer this
Suggested answer How can I declare variable in secure world memory(Trustzone-m)
  • TrustZone for Armv8-M
  • TrustZone
0 votes 264 views 3 replies Latest 15 hours ago by Oliver Beirne Answer this
Not answered Query related to function call compiled in AARCH32 execution state from AARCH64 bit space 0 votes 61 views 0 replies Started 16 hours ago by Harshit Answer this
Answered Legal transactions for AXI FIXED mode
  • AXI
  • AXI4
0 votes 416 views 2 replies Latest 19 hours ago by Utkarsh S Answer this
Not answered Arm Musca A1 - SRAM0 MPC Security attribute during boot Started 13 hours ago by Daniel Oliveira 0 replies 39 views
Suggested answer Cortex A-35 prevent fetch code allocation in cache Latest 13 hours ago by Etienne Alepins 2 replies 200 views
Suggested answer Is it possible to move up from EL0 AARCH32 to EL1 AARCH64 Latest 15 hours ago by vstehle 1 replies 282 views
Suggested answer How can I declare variable in secure world memory(Trustzone-m) Latest 15 hours ago by Oliver Beirne 3 replies 264 views
Not answered Query related to function call compiled in AARCH32 execution state from AARCH64 bit space Started 16 hours ago by Harshit 0 replies 61 views
Answered Legal transactions for AXI FIXED mode Latest 19 hours ago by Utkarsh S 2 replies 416 views