SecurCore

Arm SecurCore processors are designed specifically for high-performance and high-volume smartcard and embedded security applications. 

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Suggested answer VMSAv8-64 and spinlock 0 votes 782 views 3 replies Latest yesterday by Ciro Donnarumma Answer this
Not answered Event Recorder with STM32F0
  • Cortex-M0
  • SRAM
  • STM32 F0
  • event
0 votes 46 views 0 replies Started 2 days ago by NSharp Answer this
Answered A question aboout Monitor Vector Base Address Register(MVBAR)
  • Cortex-A9
  • TrustZone
0 votes 284 views 6 replies Latest 2 days ago by scribnote5 Answer this
Answered SysTick
  • 15 (SysTick)
0 votes 133 views 1 replies Latest 3 days ago by 42Bastian Schick Answer this
Not answered Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API
  • Cortex-A9
  • DMA Devices
  • Linux
0 votes 70 views 0 replies Started 4 days ago by eli.z Answer this
Not answered shareable domain and cache policy problem
  • Cortex-A53
  • big.LITTLE
  • l1
  • cache
  • Cortex-A
  • l2
0 votes 97 views 0 replies Started 4 days ago by zhi Answer this
Suggested answer VMSAv8-64 and spinlock Latest yesterday by Ciro Donnarumma 3 replies 782 views
Not answered Event Recorder with STM32F0 Started 2 days ago by NSharp 0 replies 46 views
Answered A question aboout Monitor Vector Base Address Register(MVBAR) Latest 2 days ago by scribnote5 6 replies 284 views
Answered SysTick Latest 3 days ago by 42Bastian Schick 1 replies 133 views
Not answered Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API Started 4 days ago by eli.z 0 replies 70 views
Not answered shareable domain and cache policy problem Started 4 days ago by zhi 0 replies 97 views