SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
0.125 mm2
0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Answered hardfault error
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0 votes 796 views 4 replies Latest 12 hours ago by 42Bastian Schick Answer this
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Answered MPS2+ Expansion ports possible frequency and usage
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  • iOS
  • Cortex-M
  • Cortex-M Prototyping System (V2M-MPS2)
0 votes 3480 views 6 replies Latest yesterday by kfzhang Answer this
Not answered There was a problem compiling the content above design start eval. 1 votes 68 views 0 replies Started 2 days ago by qinwenjian Answer this
Suggested answer Reading ETB from software
  • CoreSight ETB11
  • Cortex-A9
0 votes 2332 views 1 replies Latest 7 days ago by 42Bastian Schick Answer this
Answered hardfault error Latest 12 hours ago by 42Bastian Schick 4 replies 796 views
Suggested answer Can I run an A9 program under A53 without any modification Latest 23 hours ago by 42Bastian Schick 1 replies 750 views
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) Latest yesterday by qinwenjian 2 replies 194 views
Answered MPS2+ Expansion ports possible frequency and usage Latest yesterday by kfzhang 6 replies 3480 views
Not answered There was a problem compiling the content above design start eval. Started 2 days ago by qinwenjian 0 replies 68 views
Suggested answer Reading ETB from software Latest 7 days ago by 42Bastian Schick 1 replies 2332 views