SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
0.125 mm2
0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? 0 votes 10 views 0 replies Started 6 hours ago by jpthibault Answer this
Not answered why does LDR takes two cycle to be executed 0 votes 21 views 0 replies Started 10 hours ago by Haohao Answer this
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state?
  • Armv8-A
  • AArch32
0 votes 65 views 1 replies Latest 20 hours ago by 42Bastian Schick Answer this
Suggested answer How to Change the Non Secure VTOR (Cortex-M33)
  • TrustZone for Armv8-M
  • Trusted Execution Environment (TEE)
  • TrustZone
  • Cortex-M33
  • Armv8-M
0 votes 92 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer How to import C variable in an assembly code in a .s file
  • Cortex-M
  • cortex-m0+
  • Arm Assembly Language (ASM)
0 votes 69 views 1 replies Latest yesterday by Georgia James Answer this
Answered Watchdog timer not entering ISR
  • Cortex-A9
  • Interrupt Controller Devices
  • Cortex-A
  • Interrupt
0 votes 109 views 2 replies Latest yesterday by sherry Answer this
Not answered Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition? Started 6 hours ago by jpthibault 0 replies 10 views
Not answered why does LDR takes two cycle to be executed Started 10 hours ago by Haohao 0 replies 21 views
Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state? Latest 20 hours ago by 42Bastian Schick 1 replies 65 views
Suggested answer How to Change the Non Secure VTOR (Cortex-M33) Latest yesterday by 42Bastian Schick 1 replies 92 views
Suggested answer How to import C variable in an assembly code in a .s file Latest yesterday by Georgia James 1 replies 69 views
Answered Watchdog timer not entering ISR Latest yesterday by sherry 2 replies 109 views