SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.

Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)		  90LP
(7-track, min 1.2v, 25°C)		  40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
 74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
 0.125 mm2
 0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Suggested answer Switching from 32bit to 64bit 0 votes 124 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Not answered ETM Trace bus signal integrity
  • ETM
 0 votes 97 views 0 replies Started 2 days ago by Chandrasekar J Answer this
Answered Differences between Armv7 to Armv8? 0 votes 88056 views 8 replies Latest 2 days ago by Signorel1li Answer this
Suggested answer Cortex A-35 prevent fetch code allocation in cache 0 votes 690 views 4 replies Latest 2 days ago by flongnos Answer this
Not answered What conditions would generate the CM33 FPU underflow and input denormal exception flags?
  • Cortex-M33
 0 votes 84 views 0 replies Started 2 days ago by Ankur B Answer this
Not answered [Beginner] I would like to mod a GPM4 firmware 0 votes 2 views 0 replies Started 4 days ago by Capripot Answer this
Suggested answer Switching from 32bit to 64bit Latest yesterday by 42Bastian Schick 1 replies 124 views
Not answered ETM Trace bus signal integrity Started 2 days ago by Chandrasekar J 0 replies 97 views
Answered Differences between Armv7 to Armv8? Latest 2 days ago by Signorel1li 8 replies 88056 views
Suggested answer Cortex A-35 prevent fetch code allocation in cache Latest 2 days ago by flongnos 4 replies 690 views
Not answered What conditions would generate the CM33 FPU underflow and input denormal exception flags? Started 2 days ago by Ankur B 0 replies 84 views
Not answered [Beginner] I would like to mod a GPM4 firmware Started 4 days ago by Capripot 0 replies 2 views