SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.

Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)		  90LP
(7-track, min 1.2v, 25°C)		  40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
 74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
 0.125 mm2
 0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Not answered Make MPU be uniprocessor system 0 votes 40 views 0 replies Started 20 hours ago by 2U3 Answer this
Suggested answer Cortex-M3 Registers 0 votes 439 views 5 replies Latest yesterday by John663 Answer this
Answered System wide cache flush
  • Cortex-A35
  • Cache coherency
  • Armv8-A
  • Cache Management
 0 votes 514 views 5 replies Latest yesterday by Norbert Goldstein Answer this
Suggested answer floating point performance benchmark 0 votes 1461 views 3 replies Latest 2 days ago by 42Bastian Schick Answer this
Answered ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell 0 votes 1516 views 3 replies Latest 2 days ago by jpthibault Answer this
Not answered Trouble configuring MMU for 2MB block mapping
  • Memory Management Unit (MMU)
 0 votes 658 views 0 replies Started 3 days ago by jcal93 Answer this
Not answered Make MPU be uniprocessor system Started 20 hours ago by 2U3 0 replies 40 views
Suggested answer Cortex-M3 Registers Latest yesterday by John663 5 replies 439 views
Answered System wide cache flush Latest yesterday by Norbert Goldstein 5 replies 514 views
Suggested answer floating point performance benchmark Latest 2 days ago by 42Bastian Schick 3 replies 1461 views
Answered ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell Latest 2 days ago by jpthibault 3 replies 1516 views
Not answered Trouble configuring MMU for 2MB block mapping Started 3 days ago by jcal93 0 replies 658 views