SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
0.125 mm2
0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered NVIC_EnableIRQ : enables only one interrupt at a time? 0 votes 7 views 0 replies Started 7 hours ago by ArmAsking Answer this
Not answered How to stop coresight sink on CPU exception 0 votes 5 views 0 replies Started 8 hours ago by Sudipta Answer this
Suggested answer ARMv8 memory ordering
  • Cortex-A53
  • Armv8-A
0 votes 1012 views 5 replies Latest 9 hours ago by 42Bastian Schick Answer this
Suggested answer How does ARM11 respond to a non-secure interrupt in secure mode?
  • Arm11
  • Interrupt
0 votes 1517 views 3 replies Latest 12 hours ago by morghan Answer this
Suggested answer Unable to Download Code to Controller
  • 5 (BusFault)
  • 3 (HardFault)
  • 6 (UsageFault)
  • Cortex-M4
0 votes 416 views 8 replies Latest yesterday by ShivasWorld Answer this
Suggested answer Character recognition using NXP LPC1768 (Cortex-M3)
  • Neural Network
  • Cortex-M3
  • Arm NN
0 votes 388 views 4 replies Latest yesterday by 42Bastian Schick Answer this
Not answered NVIC_EnableIRQ : enables only one interrupt at a time? Started 7 hours ago by ArmAsking 0 replies 7 views
Not answered How to stop coresight sink on CPU exception Started 8 hours ago by Sudipta 0 replies 5 views
Suggested answer ARMv8 memory ordering Latest 9 hours ago by 42Bastian Schick 5 replies 1012 views
Suggested answer How does ARM11 respond to a non-secure interrupt in secure mode? Latest 12 hours ago by morghan 3 replies 1517 views
Suggested answer Unable to Download Code to Controller Latest yesterday by ShivasWorld 8 replies 416 views
Suggested answer Character recognition using NXP LPC1768 (Cortex-M3) Latest yesterday by 42Bastian Schick 4 replies 388 views