Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

37 µW/MHz 13 µW/MHz 
 Floorplan area
0.40 mm2
 0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

Not answered Make MPU be uniprocessor system 0 votes 44 views 0 replies Started 22 hours ago by 2U3 Answer this
Suggested answer Cortex-M3 Registers 0 votes 441 views 5 replies Latest yesterday by John663 Answer this
Answered System wide cache flush
  • Cortex-A35
  • Cache coherency
  • Armv8-A
  • Cache Management
0 votes 519 views 5 replies Latest yesterday by Norbert Goldstein Answer this
Suggested answer floating point performance benchmark 0 votes 1461 views 3 replies Latest 2 days ago by 42Bastian Schick Answer this
Answered ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell 0 votes 1516 views 3 replies Latest 2 days ago by jpthibault Answer this
Not answered Trouble configuring MMU for 2MB block mapping
  • Memory Management Unit (MMU)
0 votes 658 views 0 replies Started 3 days ago by jcal93 Answer this
Not answered Make MPU be uniprocessor system Started 22 hours ago by 2U3 0 replies 44 views
Suggested answer Cortex-M3 Registers Latest yesterday by John663 5 replies 441 views
Answered System wide cache flush Latest yesterday by Norbert Goldstein 5 replies 519 views
Suggested answer floating point performance benchmark Latest 2 days ago by 42Bastian Schick 3 replies 1461 views
Answered ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell Latest 2 days ago by jpthibault 3 replies 1516 views
Not answered Trouble configuring MMU for 2MB block mapping Started 3 days ago by jcal93 0 replies 658 views