Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

37 µW/MHz 13 µW/MHz 
 Floorplan area
0.40 mm2
 0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 28 views 0 replies Started 21 hours ago by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
0 votes 808 views 20 replies Latest 3 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 48 views 0 replies Started 3 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 53 views 0 replies Started 3 days ago by BAB Answer this
Not answered Getting processor and cache details
  • cache
  • Linux
0 votes 102 views 0 replies Started 5 days ago by karthikeyan.d Answer this
Not answered Loading cortex M1 soft processor on Pynq Processor
  • Cortex-M1
  • Cortex-M
0 votes 81 views 0 replies Started 5 days ago by Sivasankar Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 21 hours ago by jing 0 replies 28 views
Answered Binary Semaphore upset by FIQ Latest 3 days ago by 42Bastian Schick 20 replies 808 views
Not answered Identifying Generic IP Components on an Access Port Started 3 days ago by Torsten Robitzki 0 replies 48 views
Not answered Issue with WatchDog reset De-asserting Started 3 days ago by BAB 0 replies 53 views
Not answered Getting processor and cache details Started 5 days ago by karthikeyan.d 0 replies 102 views
Not answered Loading cortex M1 soft processor on Pynq Processor Started 5 days ago by Sivasankar 0 replies 81 views