Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.

Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)		  90LP
(7-track, min 1.2v, 25°C)		  40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

 37 µW/MHz 13 µW/MHz 
 Floorplan area
 0.40 mm2
  0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

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Not answered PendSV target secure state 0 votes 69 views 0 replies Started 2 days ago by Jiameng Answer this
Not answered Cache Coherence Support in CHI Specification Started 15 hours ago by JO16 0 replies 81 views
Not answered Pros and cons of activating cache in stm32F7 Started 18 hours ago by Marzi 0 replies 69 views
Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) Started yesterday by Gol 0 replies 328 views
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore Latest yesterday by BurakSeker 3 replies 1578 views
Suggested answer How to access memory more than 4GB by using 32bit ISA? Latest yesterday by smithclarkson001 4 replies 362 views
Not answered PendSV target secure state Started 2 days ago by Jiameng 0 replies 69 views