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Arm provides a range of security IP, which has been created to protect against a variety of different attacks. The range of IP includes subsystems (hardware and software) that provide platform level security as well as acceleration and offloading. Plus, a range of products for physical attack mitigation and processors with Arm TrustZone support.

Cryptography and platform security services IP

Security IP with SCA protection.

Security IP with SCA protection

Arm also have a range of cryptography and platform security services IP which has been enhanced with technology that protects against power and electromagnetic side channel analysis threats and more. This level of protection is important to applications targeted by physical security attacks.

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CryptoCell-300 Family Chip.

Arm CryptoCell-300 family

The highly efficient Arm CryptoCell-300 family is focused at providing various cryptography and platform related security services, for devices with strict power and area constraints. Use cases include home automation, smart energy and automotive.

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CryptoCell-700 Family Chip.

Arm CryptoCell-700 family

The high-performance Arm CryptoCell-700 family is focused on providing various cryptography and platform related security services, for devices serving data intensive use cases. Applications include high-end consumer electronics and enterprise devices.

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Text: arm TRUSTZONE (logo).

Processor IP

Arm processors with Arm TrustZone technology

Explore the Arm Cortex processors that integrate TrustZone technology, bringing robust security to future devices.

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TrustZone Security System IP Chip.

Other system security IP

Arm TrustZone Security System IP

Arm also have a range of Security System IP, including:

  • TrustZone Random Number Generator
  • TrustZone Full Disk Encryption
  • TrustZone Address Space Controllers

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Platform Security Architecture Certified logo

Platform Security Architecture

Find out about the Platform Security Architecture (PSA), a framework for securing a trillion devices.

Access a holistic set of resources to guide security design and learn about the independent security evaluation and certification scheme - PSA Certified.

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Community Forums

Answered TF-M, how to sign an image.bin in a multi-image configuration?
  • Trusted Firmware-M
  • Cortex-M33
0 votes 234 views 1 replies Latest 9 days ago by Cristiano_Ro Answer this
Answered Non Secure malicious access handling... 0 votes 378 views 4 replies Latest 18 days ago by TexCorJC Answer this
Answered cpsid from non-secure triggers SecureFault
  • ARMv8 Exception Model
  • CoreLink SSE-200 Subsystem
  • TrustZone
0 votes 525 views 3 replies Latest 1 months ago by 42Bastian Schick Answer this
Not answered Why have a IDAU/SAU when one has a MPC 0 votes 307 views 0 replies Started 1 months ago by Chris Daniels Answer this
Suggested answer Switching from 32bit to 64bit 0 votes 3792 views 2 replies Latest 3 months ago by Zenon Xiu (修志龙) Answer this
Answered Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception
  • Real Time Operating Systems (RTOS)
  • Trusted Firmware-M
  • TrustZone for Armv8-M
  • Armv8-M
0 votes 2097 views 3 replies Latest 4 months ago by Michael Jung Answer this
Answered TF-M, how to sign an image.bin in a multi-image configuration? Latest 9 days ago by Cristiano_Ro 1 replies 234 views
Answered Non Secure malicious access handling... Latest 18 days ago by TexCorJC 4 replies 378 views
Answered cpsid from non-secure triggers SecureFault Latest 1 months ago by 42Bastian Schick 3 replies 525 views
Not answered Why have a IDAU/SAU when one has a MPC Started 1 months ago by Chris Daniels 0 replies 307 views
Suggested answer Switching from 32bit to 64bit Latest 3 months ago by Zenon Xiu (修志龙) 2 replies 3792 views
Answered Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception Latest 4 months ago by Michael Jung 3 replies 2097 views