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Arm provides a range of security IP, which has been created to protect against a variety of different attacks. The range of IP includes subsystems (hardware and software) that provide platform level security as well as acceleration and offloading. Plus, a range of products for physical attack mitigation and processors with Arm TrustZone support.

Cryptography and platform security services IP

Security IP with SCA protection.

Security IP with SCA protection

Arm also have a range of cryptography and platform security services IP which has been enhanced with technology that protects against power and electromagnetic side channel analysis threats and more. This level of protection is important to applications targeted by physical security attacks.

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CryptoCell-300 Family Chip.

Arm CryptoCell-300 family

The highly efficient Arm CryptoCell-300 family is focused at providing various cryptography and platform related security services, for devices with strict power and area constraints. Use cases include home automation, smart energy and automotive.

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CryptoCell-700 Family Chip.

Arm CryptoCell-700 family

The high-performance Arm CryptoCell-700 family is focused on providing various cryptography and platform related security services, for devices serving data intensive use cases. Applications include high-end consumer electronics and enterprise devices.

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Text: arm TRUSTZONE (logo).

Processor IP

Arm processors with Arm TrustZone technology

Explore the Arm Cortex processors that integrate TrustZone technology, bringing robust security to future devices.

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TrustZone Security System IP Chip.

Other system security IP

Arm TrustZone Security System IP

Arm also have a range of Security System IP, including:

  • TrustZone Random Number Generator
  • TrustZone Full Disk Encryption
  • TrustZone Address Space Controllers

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Platform Security Architecture Certified logo

Platform Security Architecture

Find out about the Platform Security Architecture (PSA), a framework for securing a trillion devices.

Access a holistic set of resources to guide security design and learn about the independent security evaluation and certification scheme - PSA Certified.

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Resources

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Community Forums

Suggested answer Switching from 32bit to 64bit 0 votes 3010 views 2 replies Latest 1 months ago by Zenon Xiu (修志龙） Answer this
Answered Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception
  • Real Time Operating Systems (RTOS)
  • Trusted Firmware-M
  • TrustZone for Armv8-M
  • Armv8-M
 0 votes 1181 views 3 replies Latest 2 months ago by Michael Jung Answer this
Answered The Monitor
  • TrustZone
 0 votes 5916 views 4 replies Latest 2 months ago by yufeifei Answer this
Not answered Are the IDAU NS and NSC signals assumed to be mutually exclusive? 0 votes 642 views 0 replies Started 2 months ago by kappajacko Answer this
Discussion SAU vs. IDAU in a System with Multiple Masters
  • Security
  • TrustZone
  • Armv8-M
 0 votes 11423 views 5 replies Latest 2 months ago by Chris Reed Answer this
Suggested answer Arm Musca A1 - SRAM0 MPC Security attribute during boot
  • Musca-A
  • TrustZone for Armv8-M
  • CoreLink SSE-200
 0 votes 3090 views 2 replies Latest 3 months ago by Daniel Oliveira Answer this
Suggested answer Switching from 32bit to 64bit Latest 1 months ago by Zenon Xiu (修志龙） 2 replies 3010 views
Answered Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception Latest 2 months ago by Michael Jung 3 replies 1181 views
Answered The Monitor Latest 2 months ago by yufeifei 4 replies 5916 views
Not answered Are the IDAU NS and NSC signals assumed to be mutually exclusive? Started 2 months ago by kappajacko 0 replies 642 views
Discussion SAU vs. IDAU in a System with Multiple Masters Latest 2 months ago by Chris Reed 5 replies 11423 views
Suggested answer Arm Musca A1 - SRAM0 MPC Security attribute during boot Latest 3 months ago by Daniel Oliveira 2 replies 3090 views