What

Getting Started

Arm CryptoCell-312 is a comprehensive security solution for low power, low area designs.

It enhances SoC-level security with features protecting the authenticity, integrity and confidentiality of code and data belonging to different stakeholders (for example the chip maker, device maker, service provider and user).

The Armv8-M inherent capability serves as a Root of Trust (RoT), isolating assets in one execution environment and preventing them from being exploited through software vulnerabilities in another environment.

As the lock diagram on the right illustrates, CryptoCell-312 both complements the isolation and builds on it. It provides additional trust anchors and security mechanisms to assure the execution state is safe (for a given threat model).

These mechanisms include: persistent storage of secrets, rollback prevention, validation of loaded software, validation of software updates, cryptography, True Random Number Generation, strong authentication of parties prior to giving them access to resources and more.


Simplifying the design of secure IoT systems

Free on-demand training webinar about Arm CryptoCell

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A locking device.

Balancing the right security solution

A security solution balances the right set of measures so you can effectively address the target threat model, without affecting the usability of the product. It’s important to ensure that the user experience is not impacted, while maintaining the overall power and area budget.

The certifiable CryptoCell-312 solution allows you to tick all the boxes, using hardware, on-chip software and a rich set of off-device tools, addressing various manufacturing and ecosystem enablement processes (e.g. certificates generation, code encryption and more).

All of the CryptoCell-312 components are provided in source code format.

 

Validating if a system works.

Enabling a full set of security services

Designed with all relevant, state-of-the-art security related standards in mind, CryptoCell-312 supports the following functional features:

  • Symmetric and asymmetric cryptography.
  • True Random Number Generator.
  • Device lifecycle state management.
  • Root of Trust access policy enforced by hardware means.
  • Root of Trust ownership model allowing multiple entities to own different trust anchor, removing the need for default trust between entities along the value chain.
  • Keys and assets provisioning, management and isolation, across different device operational scenarios, both in-factory and in the field.
  • Software image validation and optional decryption both at boot time and update time.
  • Secure debug and design for test.

The key benefits of CryptoCell-312

CoreLink SSE-200 Subsystem Block Diagram.

  • CryptoCell-312 allows design teams to get security right.
  • Free up tens of man years and enabling design teams to focus on their real differentiation.
  • Validated and integrated with SSE-200, SIE-200Cortex-M23, Cortex-M33 and v8-M software stack.

  • CryptoCell-312 provides a rich set of platform security services, enabling brand-name protection, IP protection (improved monetization of R&D investment) and various use cases across all IoT markets.
  • CryptoCell-312 increases performance by 10-15x (when compared to software only operations) on cryptography tasks.

Hardware Performance

Hardware performance: based on hardware only, zero ABH read/write delay and 1KB chunks of data

   Hardware performance, including DMA and AHB (Bits/clock)
HASH SHA256
 5.88
AES (128b keys)
 3.07
CHACHA20  6.18

Frequency

CryptoCell-312 gets to 200MHz on TSMC CLN40ULP (7T).

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Answered Where do I find presentations and photos from SC'18? 2 votes 1206 views 0 replies Started 8 months ago by John Linford Answer this
Not answered multi core debug interface for ARM CM3 0 votes 9 views 0 replies Started 5 hours ago by Madduri Answer this
Suggested answer Trying to set the IDE to recognize additional RAM available from a larger external DDRAM designed into current design 0 votes 63 views 2 replies Latest 5 hours ago by Larry Shilkoff Answer this
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Suggested answer Function with different types of arguments 0 votes 398 views 3 replies Latest 9 hours ago by ²erik malund Answer this
Not answered wrong page size in STM32F0xx_256.FLM DFP flash algo for STM32F09x 0 votes 40 views 0 replies Started 10 hours ago by rµ75 Answer this
Answered Where do I find presentations and photos from SC'18? Started 8 months ago by John Linford 0 replies 1206 views
Not answered multi core debug interface for ARM CM3 Started 5 hours ago by Madduri 0 replies 9 views
Suggested answer Trying to set the IDE to recognize additional RAM available from a larger external DDRAM designed into current design Latest 5 hours ago by Larry Shilkoff 2 replies 63 views
Not answered Getting started with mbedTLS Started 6 hours ago by techguyz 0 replies 26 views
Suggested answer Function with different types of arguments Latest 9 hours ago by ²erik malund 3 replies 398 views
Not answered wrong page size in STM32F0xx_256.FLM DFP flash algo for STM32F09x Started 10 hours ago by rµ75 0 replies 40 views