Text: arm TRUSTZONE (logo).

Arm TrustZone Technology

Arm TrustZone technology offers an efficient, system-wide approach to security with hardware-enforced isolation built into the CPU. It provides the perfect starting point for establishing a device root of trust based on Platform Security Architecture (PSA) guidelines.

The family of TrustZone technologies can be integrated into any Arm Cortex-A processor or processor based on the Armv7-A and Armv8-A architecture, and Cortex-M processors built on the Armv8-M architecture.

TrustZone for Cortex-A

TrustZone is used on billions of application processors to protect high-value code and data for diverse use cases including authentication, payment, content protection and enterprise. On application processors, TrustZone is frequently used to provide a security boundary for a GlobalPlatform Trusted Execution Environment.

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TrustZone for Cortex-M

The Armv8-M architecture extends TrustZone to Cortex-M, enabling robust levels of protection. TrustZone for Armv8-M has the same high-level features as TrustZone on application processors, with the key benefit that switching between Secure and Non-secure worlds is done in hardware for faster transitions and improved power efficiency.

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TrustZone for Armv8-A vs. TrustZone for Armv8-M

Feature/Architecture TrustZone for Armv8-A TrustZone for Armv8-M 
Additional security states SEL0 - Trusted Apps SEL1 - Trusted OS EL3 - Trusted Boot and Firmware (Armv8-A) Secure thread - Trusted code/data Secure handler - Trusted device drivers, RTOS, Library managers...
Secure interrupts Yes Yes (Fast) 
State transition (Boundary crossing) Software transition Hardware transition (Fast) 
Memory management Virtual memory MMU with secure attributes Secure Attribution Unit (SAU) and MPU memory partitions
System interconnect security Yes Yes
Secure code, data and memory Yes Yes
Trusted boot  Yes Yes
Software Arm Trusted Firmware (and third-party TEEs)  Arm Keil MDK, CMSIS, Arm Mbed OS and third-party software 

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Community Blogs

Community Forums

Discussion What is the top level difference in features between Cortex-M33 and Cortex-M4?
  • Cortex-M23
  • Trace
  • ACE
  • AXI
  • CHI
  • Security
  • Cortex-M3
  • Cortex-M
  • TrustZone
  • Cortex-M33
  • Armv8-M
  • Cortex-M4
  • Internet of Things (IoT)
  • AHB
  • Interrupt
0 votes 10783 views 1 replies Latest 2 months ago by bodybeacon Answer this
Not answered Use DS-5 MPS2_CM33 FVP in non-secure mode ? 0 votes 996 views 0 replies Started 2 months ago by ilchang Answer this
Suggested answer Calling non-secure Reset Handler from Secure main
  • Cortex-M33
  • Armv8-M
0 votes 1795 views 1 replies Latest 2 months ago by Radhika Raghavendran Answer this
Suggested answer SAU configuration failure
  • TrustZone for Armv8-M
  • Cortex-M33
0 votes 1659 views 1 replies Latest 2 months ago by Radhika Raghavendran Answer this
Suggested answer Context protection when calling a secure function(NSC) in a non-secure interrupt function 0 votes 6340 views 10 replies Latest 6 months ago by Yang Zhang Answer this
Suggested answer How to place FreeRTOS in secure memory and the user tasks in non-secure memory?
  • TrustZone
  • Armv8-M
0 votes 16218 views 21 replies Latest 6 months ago by Joseph Yiu Answer this
Discussion What is the top level difference in features between Cortex-M33 and Cortex-M4? Latest 2 months ago by bodybeacon 1 replies 10783 views
Not answered Use DS-5 MPS2_CM33 FVP in non-secure mode ? Started 2 months ago by ilchang 0 replies 996 views
Suggested answer Calling non-secure Reset Handler from Secure main Latest 2 months ago by Radhika Raghavendran 1 replies 1795 views
Suggested answer SAU configuration failure Latest 2 months ago by Radhika Raghavendran 1 replies 1659 views
Suggested answer Context protection when calling a secure function(NSC) in a non-secure interrupt function Latest 6 months ago by Yang Zhang 10 replies 6340 views
Suggested answer How to place FreeRTOS in secure memory and the user tasks in non-secure memory? Latest 6 months ago by Joseph Yiu 21 replies 16218 views