Text: arm TRUSTZONE (logo).

Arm TrustZone Technology

Arm TrustZone technology offers an efficient, system-wide approach to security with hardware-enforced isolation built into the CPU. It provides the perfect starting point for establishing a device root of trust based on Platform Security Architecture (PSA) guidelines.

The family of TrustZone technologies can be integrated into any Arm Cortex-A processor or processor based on the Armv7-A and Armv8-A architecture, and Cortex-M processors built on the Armv8-M architecture.

TrustZone for Cortex-A

TrustZone is used on billions of application processors to protect high-value code and data for diverse use cases including authentication, payment, content protection and enterprise. On application processors, TrustZone is frequently used to provide a security boundary for a GlobalPlatform Trusted Execution Environment.

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TrustZone for Cortex-M

The Armv8-M architecture extends TrustZone to Cortex-M, enabling robust levels of protection. TrustZone for Armv8-M has the same high-level features as TrustZone on application processors, with the key benefit that switching between Secure and Non-secure worlds is done in hardware for faster transitions and improved power efficiency.

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TrustZone for Armv8-A vs. TrustZone for Armv8-M

Feature/Architecture TrustZone for Armv8-A TrustZone for Armv8-M 
Additional security states SEL0 - Trusted Apps SEL1 - Trusted OS EL3 - Trusted Boot and Firmware (Armv8-A) Secure thread - Trusted code/data Secure handler - Trusted device drivers, RTOS, Library managers...
Secure interrupts Yes Yes (Fast) 
State transition (Boundary crossing) Software transition Hardware transition (Fast) 
Memory management Virtual memory MMU with secure attributes Secure Attribution Unit (SAU) and MPU memory partitions
System interconnect security Yes Yes
Secure code, data and memory Yes Yes
Trusted boot  Yes Yes
Software Arm Trusted Firmware (and third-party TEEs)  Arm Keil MDK, CMSIS, Arm Mbed OS and third-party software 

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Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

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Community Blogs

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Silicon Labs’ multiprotocol Series 2 wireless platform adds cutting-edge se

Read more about Silicon Labs Arm Cortex-M33 based low-power wireless family with support for Bluetooth 5.1, Zigbee 3.0 and Thread.

5 months ago by Kobus Marneweck
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Anchoring TrustZone with SRAM PUF

Let's take a look at how SRAM PUF, enabled through software, is a powerful addition to the security features offered by Arm TrustZone.

5 months ago by Marten van Hulst
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STMicroelectronics enhances STM32 portfolio security with new Arm…

The first ST product family to incorporate TrustZone technology for Arm Cortex-M processors, making possible system-wide software security and a new level of trust for embedded devices.

a year ago by Kobus Marneweck
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NXP enhances embedded security and signal processing with new Arm…

NXP announces two new chip families based on the Arm Cortex-M33 processor, one of the first Cortex-M processors with TrustZone security technology, bringing a new level of trust to embedded systems.

1 years ago by Kobus Marneweck
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Enhancing embedded device security with new TrustZone-enabled microcontroll

The introduction of Nuvoton’s M2351 microcontroller, including the Arm Cortex-M23 processor brings a new level of trust and security to embedded systems.

1 years ago by Kobus Marneweck
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Microchip release first Arm Cortex-M23 based chip bringing new levels of…

Microchip unveiled two MCU families, the SAM L11 with TrustZone for Armv8-M, for applications requiring embedded security, and SAM L10 for low-power and touch capabilities.

1 years ago by Kobus Marneweck

Community Forums

Discussion What is the top level difference in features between Cortex-M33 and Cortex-M4?
  • Cortex-M23
  • Trace
  • ACE
  • AXI
  • CHI
  • Security
  • Cortex-M3
  • Cortex-M
  • TrustZone
  • Cortex-M33
  • Armv8-M
  • Cortex-M4
  • Internet of Things (IoT)
  • AHB
  • Interrupt
 0 votes 8602 views 1 replies Latest 15 days ago by bodybeacon Answer this
Not answered Use DS-5 MPS2_CM33 FVP in non-secure mode ? 0 votes 281 views 0 replies Started 19 days ago by ilchang Answer this
Suggested answer Calling non-secure Reset Handler from Secure main
  • Cortex-M33
  • Armv8-M
 0 votes 749 views 1 replies Latest 27 days ago by Radhika Raghavendran Answer this
Suggested answer SAU configuration failure
  • TrustZone for Armv8-M
  • Cortex-M33
 0 votes 637 views 1 replies Latest 27 days ago by Radhika Raghavendran Answer this
Suggested answer Context protection when calling a secure function(NSC) in a non-secure interrupt function 0 votes 4523 views 10 replies Latest 4 months ago by Yang Zhang Answer this
Suggested answer How to place FreeRTOS in secure memory and the user tasks in non-secure memory?
  • TrustZone
  • Armv8-M
 0 votes 12981 views 21 replies Latest 4 months ago by Joseph Yiu Answer this
Discussion What is the top level difference in features between Cortex-M33 and Cortex-M4? Latest 15 days ago by bodybeacon 1 replies 8602 views
Not answered Use DS-5 MPS2_CM33 FVP in non-secure mode ? Started 19 days ago by ilchang 0 replies 281 views
Suggested answer Calling non-secure Reset Handler from Secure main Latest 27 days ago by Radhika Raghavendran 1 replies 749 views
Suggested answer SAU configuration failure Latest 27 days ago by Radhika Raghavendran 1 replies 637 views
Suggested answer Context protection when calling a secure function(NSC) in a non-secure interrupt function Latest 4 months ago by Yang Zhang 10 replies 4523 views
Suggested answer How to place FreeRTOS in secure memory and the user tasks in non-secure memory? Latest 4 months ago by Joseph Yiu 21 replies 12981 views