TrustZone technology for Armv8-A

Architecture of Trusted Execution Environment Information Slide.

Arm TrustZone is used on billions of applications' processors to protect high-value code and data. It is frequently used to provide a security boundary for a GlobalPlatform Trusted Execution Environment.

TrustZone is built on Secure and Non-secure worlds that are hardware separated. The partitioning of the two worlds is achieved by hardware logic present in the AMBA bus fabric, peripherals and processors.

In order to implement a Secure state in the SoC, trusted software (Trusted OS) needs to be developed to make use of the protected assets. This code typically implements trusted boot, the Secure world switch monitor, a small trusted OS and trusted apps. The combination of TrustZone based hardware isolation, trusted boot and a trusted OS make up a Trusted Execution Environment (TEE), which can be used alongside other security technology.

Learn more about the GlobalPlatform TEE.

Resources

Supporting documentation and resources for developing with TrustZone for Armv8-A

Architecture overview

Documentation demonstrating the fundamentals to the Armv8-A architecture.

Learn more

Specificationlibrary

Specifications and technical documents, which are subject to the Global Platform TEE.

Learn more

TrustZone-based TEE and FIDO authentication

White paper explaining how to secure the future of authentication with Arm TrustZone-based Trusted Execution Environment (TEE) and Fast Identity Online (FIDO).

Download

Software and tools

Explore software and tools available from Arm to maximize the capabilities of your TrustZone-enabled device

Arm Development Studio

Flagship embedded tool suite where multicore scalability meets enhanced productivity, enabled by CMSIS.

Learn more

Trusted Firmware-A

Trusted Firmware-A (TF-A) provides a reference implementation of Secure world software for Armv7-A and Armv8-A.

Learn more

Training

Explore training materials for TrustZone, delivered by the world's most experienced Arm technology trainers

Arm TrustZone technology training

This course provides platform developers a complete overview of designing trusted systems with Arm TrustZone, introducing the privilege model and memory separation features of the Armv8-A architecture.

Learn more

TrustZone forArmv8-A

This course provides an insight into the purpose and functionality of Arm TrustZone for Armv8-A technology, explaining some of the use cases for TrustZone and the architectural features.

Learn more

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Suggested answer How to access memory more than 4GB by using 32bit ISA?
  • Memory Access Instructions
0 votes 558 views 5 replies Latest 7 hours ago by Martin Weidmann Answer this
Suggested answer Saving processor state for power-down and resume
  • Thumb
  • Cortex-M4
0 votes 79 views 1 replies Latest 11 hours ago by 42Bastian Schick Answer this
Suggested answer adc read
  • Cortex-M0
0 votes 101 views 1 replies Latest 12 hours ago by 42Bastian Schick Answer this
Not answered How to write values ​​from secure code to non-secure memory.
  • TrustZone for Armv8-M
0 votes 132 views 0 replies Started yesterday by Lars Answer this
Not answered Cache Coherence Support in CHI Specification 0 votes 190 views 0 replies Started 2 days ago by JO16 Answer this
Not answered Pros and cons of activating cache in stm32F7 0 votes 164 views 0 replies Started 2 days ago by Marzi Answer this
Suggested answer How to access memory more than 4GB by using 32bit ISA? Latest 7 hours ago by Martin Weidmann 5 replies 558 views
Suggested answer Saving processor state for power-down and resume Latest 11 hours ago by 42Bastian Schick 1 replies 79 views
Suggested answer adc read Latest 12 hours ago by 42Bastian Schick 1 replies 101 views
Not answered How to write values ​​from secure code to non-secure memory. Started yesterday by Lars 0 replies 132 views
Not answered Cache Coherence Support in CHI Specification Started 2 days ago by JO16 0 replies 190 views
Not answered Pros and cons of activating cache in stm32F7 Started 2 days ago by Marzi 0 replies 164 views