Getting Started

For the Internet of Things (IoT), one size does not fit all. IoT is about diverse applications, nodes, and sensors, which lead to diversity in end-node requirements and price points. IoT means billions of connected devices, some of these devices will be addressed by off-the-shelf designs while other applications will require customized SoCs and precise sensor integration.

The Arm subsystem supports IoT market growth by reducing development risk and enabling companies to quickly create products.


Technical Reference Manual

For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

About CoreLink SSE-100

The Arm subsystem supports IoT market growth by reducing development risk and enabling companies to quickly create products. The CoreLink SSE-100 subsystem includes open-source software libraries, integrated with the Arm mbed OS. Arm provides a complete IoT reference system that reduces the complexity and risk of an SoC design. The CoreLink SSE-100 subsystem features a range of peripherals and interfaces, including a Flash Controller for TSMC’s embedded Flash memory. It is specifically designed for use with Arm Cortex-M processors. It can be integrated with wireless networking standards such as Wi-Fi and 802.15.4. The system design enhances two key features for IoT solutions: optimized power consumption and improved levels of security, with seamless mbed OS integration.

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CoreLink SSE-100 subsystem example diagram

The CoreLink SSE-100 subsystem contains the foundation IP necessary in most IoT endpoints. Pre-validated using the same methodology and processes that are used to ensure the quality of Arm IP, it reduces the design risk and accelerates SoC development projects for IoT nodes.

Key features

Interconnect

This AHB-lite multilayer crossbar interconnect links the system's main components. It features expansion ports to plug external master or slave components.

The integrated APB bridge also enables rapid connection of additional peripherals.

SRAM Controller

This controller attaches a configurable amount of SRAM to the system. It supports several instances of SRAM to precisely tune which ones can be powered-down or placed in retention mode.

Power Management 

This takes care of reducing the power consumption of the system to make sure that IoT devices built with this subsystem draw less current.

Cortex-M3 processor

The CoreLink SSE-100 subsystem connects to a Cortex-M3 processor. The Cortex-M3 is used in many current IoT devices, and is a good choice to run complex software stacks like mbed OS.

Learn more about the Cortex-M3

Artisan Libraries

In order to meet the power requirements of IoT endpoints, it is necessary to use low-power libraries and SRAMs with different power modes, including support for retaining data across multiple modes.

Learn more about Arm libraries

CMSDK

The Cortex-M System Design Kit is essential to many systems, including the IoT subsystem. In addition to a configurable interconnect, it consists of many bridges and interfaces.

Learn more about the CMSDK

mbed OS

Software development is a very large part of the design time. The IoT subsystem has been developed in sync with mbed OS, and all hardware drivers are already available when you download the software stack.

This makes an SoC based on the IoT subsystem very attractive to software developers, who can start creating applications and use all the features of mbed OS right away.

Learn more about mbed OS

Security

mbed OS brings in a range of features that allow developers to ensure that their product is secure.

You can also opt for a strong HW-based security environment, with the lowest possible attack surface, encryption acceleration, and true random number generation (TRNG).

Flash Cache performance

As Flash read accesses are slow and power hungry, the Flash Cache of the IoT subsystem is a key feature to reduce the overall power consumption and increase performance of the system.

Its size has been determined by a study of system performance to reduce the number of Flash read accesses as much as possible. A further reduction is achieved by using a wide 128 bit data bus at the Flash Controller level.

A battery that is durable.

Key benefits

Low power consumption

Thanks to its built-in Flash Controller, the CoreLink SSE-100 subsystem can connect to an embedded Flash and lead to single-chip designs that consume less energy than multi-chip solutions.

Additionally, the CoreLink SSE-100 subsystem includes an integrated cache which allows up to 99% flash power consumption reduction, by reducing the number of Flash fetches.

3 engineers and 3 months to tape-out!

At Arm TechCon 2015, Arm demonstrated the Beetle test chip. Using the CoreLink SSE-100 subsystem, this test chip was assembled and taped-out in 3 months by a dedicated team of 3 engineers. First time success!

EETimes article

Beetle Development Board.

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Suggested answer DS-5 bare metal wait error after run "debug" Latest 7 hours ago by Ronan Synnott 13 replies 16425 views
Suggested answer Creating an Assembly project in DS IDE 2020 Latest 7 hours ago by Ronan Synnott 1 replies 957 views
Suggested answer Include source file in DS 2020 Latest 7 hours ago by Ronan Synnott 1 replies 975 views
Suggested answer Debug Problem with STM32L011 Latest 12 hours ago by Robert McNamara 1 replies 76 views
Suggested answer Problems with setting up the event recorder for LPC1769 Latest 19 hours ago by coldspark 2 replies 99 views
Not answered How to check if Neon instructions are used? Started 22 hours ago by DanijelDomazet 0 replies 33 views