About CoreLink SSE-200

The Arm CoreLink SSE-200 subsystem is the fastest way to get your next project to tape-out and to create successful secure IoT chips. It integrates the core components of your system in a validated foundation that you can trust.

The CoreLink SSE-200 subsystem is a component of the Corstone-200 and Corstone-201 foundation IP.

Corstone Foundation IP

The CoreLink SSE-200 subsystem is included in the Corstone-200 and Corstone-201 foundation IP - the fastest secure solution to lead in the IoT market.


Technical Reference Manual

This document is written for system designers, system integrators, and programmers who are designing or
programming a SoC using SSE-200.

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The flexible architecture for your future secure IoT designs

Building security into an embedded system and integrating all the necessary components take a significant amount of time and effort. The CoreLink SSE-200 subsystem aims to make this difficult process easier, by integrating and validating Arm IP in one system. The CoreLink SSE-200 subsystem is based on a two-core structure, and integrates features you would expect to find in best-in-class IoT chips. 

The CoreLink SSE-200 subsystem integrates the following Arm IP:

  • Arm Cortex-M33 processor
  • Arm CoreLink SIE-200
  • Instruction caches with Arm TrustZone support
  • Power infrastructure components
  • CoreSight SoC
  • Arm TrustZone CryptoCell (option)

Get security right

It is a challenge to implement security in a device with tight constraints on size and power consumption. Arm has designed security into the heart of the CoreLink SSE-200 subsystem, with  different components responsible for device security, communication security and lifecycle security.

Yet security for the hardware components alone is not enough. The CoreLink SSE-200 subsystem has security integrated at the software level. This ensures you start from a good foundation and can build a very secure overall system. You benefit from our strong security expertise, which has been gathered and harnessed to create the CoreLink SSE-200 subsystem and its constituents: 

  • Arm TrustZone security technology
  • Arm CoreLink SIE-200 system IP
  • Arm TrustZone CryptoCell
  • Secure components of Mbed OS

Key features

The SSE-200 subsystem gives you the flexibility to build your own system, so it is the right size and tailored for your application. Several blocks in the CoreLink SSE-200 subsystem are optional. It is possible to select:

  • One of two Cortex-M33 cores
  • TrustZone CryptoCell
  • Cordio Radio
  • Verified configuration options are also available
  • Processor configuration and frequencies options
  • RAM sizes and partitioning
  • Cache sizes

Different IoT applications have different requirements, but a very common feature is the need to reduce the power consumption. Reducing power consumption is imperative in IoT designs – if this is ignored, the result could be billions of IoT devices wasting energy.

A dual-core system allows the background OS to run on the energy efficient core, while the second high performance core can be turned on for more demanding tasks. This partitioning delivers significant performance bursts while keeping the average power consumption very low.

Caches have also been integrated in the system to reduce power consuming accesses to the Flash, and the always-on domain allows the application to power-off the system while keeping synchronization.

Key benefits

  • Bring an ARM®v8 Cortex®-M-based chip to market 6-12 months faster than designing from scratch.
  • The subsystem is pre-integrated and verified to allow you to focus your engineering resource on differentiation.
  • Start development straight away, with ARM® mbed™ OS out-of-box software.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

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0 votes 1359 views 3 replies Latest 11 hours ago by BurakSeker Answer this
Not answered reading data in http client application 0 votes 40 views 0 replies Started 13 hours ago by giomaca Answer this
Suggested answer Keil uVision Error L6218E: Undefined Symbol APBPrescTable (referred from stm32f4xx_hal_rcc.o)
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0 votes 2174 views 9 replies Latest 14 hours ago by Westonsupermare Pier Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 64 views 0 replies Started 16 hours ago by Kiran bhat Answer this
Answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 2143 views
Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) Started 10 hours ago by Gol 0 replies 44 views
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore Latest 11 hours ago by BurakSeker 3 replies 1359 views
Not answered reading data in http client application Started 13 hours ago by giomaca 0 replies 40 views
Suggested answer Keil uVision Error L6218E: Undefined Symbol APBPrescTable (referred from stm32f4xx_hal_rcc.o) Latest 14 hours ago by Westonsupermare Pier 9 replies 2174 views
Not answered STM32F769i-Discovery IP Camera Interface Started 16 hours ago by Kiran bhat 0 replies 64 views