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Invalid Date NaN, NaN
However, the cortex M3 RTL source file(s) is obfuscated (cortexm3ds_logic.v) or encrypted (cortexm3.v). ... I understand that they are synthesizable but is it possible to view the Verilog sources a...
Invalid Date NaN, NaN
I have a question about AHB protocal. ... I had read "AHB 5.0 Specification" and "AHB 2.0 Specification". ... Compared these specifications, the following pictures about BUSY state are from "AHB 5....
Invalid Date NaN, NaN
hello I want to know how to reset axi master can cause axi bus  matrix deadlock in soc design,and how to aviod or detect this condition?
Invalid Date NaN, NaN
Can you please share the ideal behavior of RLAST in ACE5 two-part DVM transaction? ... Is there a value for RLAST to be fixed? ... If possible, please provide additional details about the recogniti...
Invalid Date NaN, NaN
I'm trying PIE/POE feature provided by v8.9, and I notice Linux becomes compatible with this feature since v6.5. ... Thus I use scripts provided here to setup the environment. ... However, when I e...
Invalid Date NaN, NaN
1. When a Manager issues a write request, it must be able to provide all write data for that transaction, without dependency on other transactions from that Manager. ... 2. When a Manager has issue...
Invalid Date NaN, NaN
I have been using the DesignStart Cortex M3 for several years in the courses I teach, but I cannot get it to work with any version of Vivado newer than 2022.1.  Being stuck at an old versio...
Invalid Date NaN, NaN
Regarding the AHB5 exclusive access monitor, there is a paragraph that reads: ... Can it be understood as ' hexokay_m signal is tied 0 'in the following figure? ... Because during integration, the ...
Invalid Date NaN, NaN
I'm trying to understand how I would be able to connect a Mali-G78AE to the CMN-600AE.  The I/O coherent requester nodes are able to support 3 channels each and the G78AE can have ...
Invalid Date NaN, NaN
Hello, I am using the AXI4 protocol and I wonder if I can create a read-modify-write access just by modifying the write_strobes signals. ... Is it possible, or do write strobes signals always have ...
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ARM Cortex-M3 DesignStart FPGA Xilinx Edition and EVAL RTL sources

Hello, I downloaded the DesignStart packages for the FPGA Xilinx edition (Arm Cortex-M on FPGA) and the EVAL versions. However, the cortex M3 RTL source file(s) is obfuscated (cortexm3ds_logic.v) or encrypted (cortexm3.v). I understand that they are synthesizable but is it possible to view the Verilog sources at all or are these "free" IP cores only meant to be used without modification or access to the sources?  If it is possible to access the actual Verilog source files for the M3 processor, how might I be able to do that? Thanks!

SoC Design and Simulation forum

The BUSY state of HTRANS, compared AHB 2.0 with AHB 5.0

Hi, I have a question about AHB protocal. I had read "AHB 5.0 Specification" and "AHB 2.0 Specification". Compared these specifications, the following pictures about BUSY state are from "AHB 5.0 Specification",but cannot find the corresponding information in "AHB 2.0 Specification". So I would like to ask whether the BUSY(htrans) signal has the same behaviors in AHB 2.0?  Do BUSY states of HTRANS between AHB 2.0 and AHB 5.0 keep the same bus behaviors? If not, what is the difference about them?   Thanks Regards E.K.

SoC Design and Simulation forum

how to reset axi master can cause axi bus deadlock in soc design

hello I want to know how to reset axi master can cause axi bus  matrix deadlock in soc design,and how to aviod or detect this condition? I use nic400 matrix bus.

SoC Design and Simulation forum

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