About CoreLink SSE-200

The Arm CoreLink SSE-200 subsystem is one of the fastest ways to get your next project to tape-out and to create successful secure IoT chips. It integrates the core components of your system in a validated foundation that you can trust.

The CoreLink SSE-200 subsystem is a component of the Corstone-200 and Corstone-201 foundation IP.

Corstone Foundation IP

The CoreLink SSE-200 subsystem is included in the Corstone-200 and Corstone-201 foundation IP - the fastest secure solution to lead in the IoT market.


Technical Reference Manual

This document is written for system designers, system integrators, and programmers who are designing or
programming a SoC using SSE-200.

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The flexible architecture for your future secure IoT designs

Building security into an embedded system and integrating all the necessary components take a significant amount of time and effort. The CoreLink SSE-200 subsystem aims to make this difficult process easier, by integrating and validating Arm IP in one system. The CoreLink SSE-200 subsystem is based on a two-core structure, and integrates features you would expect to find in best-in-class IoT chips. 

The CoreLink SSE-200 subsystem integrates the following Arm IP:

  • Arm Cortex-M33 processor
  • Arm CoreLink SIE-200
  • Instruction caches with Arm TrustZone support
  • Power infrastructure components
  • CoreSight SoC
  • Arm TrustZone CryptoCell (option)

Get security right

It is a challenge to implement security in a device with tight constraints on size and power consumption. Arm has designed security into the heart of the CoreLink SSE-200 subsystem, with  different components responsible for device security, communication security and lifecycle security.

Yet security for the hardware components alone is not enough. The CoreLink SSE-200 subsystem has security integrated at the software level. This ensures you start from a good foundation and can build a very secure overall system. You benefit from our strong security expertise, which has been gathered and harnessed to create the CoreLink SSE-200 subsystem and its constituents: 

  • Arm TrustZone security technology
  • Arm CoreLink SIE-200 system IP
  • Arm TrustZone CryptoCell
  • Secure components of Mbed OS

Key features

The SSE-200 subsystem gives you the flexibility to build your own system, so it is the right size and tailored for your application. Several blocks in the CoreLink SSE-200 subsystem are optional. It is possible to select:

  • One of two Cortex-M33 cores
  • TrustZone CryptoCell
  • Verified configuration options are also available
  • Processor configuration and frequencies options
  • RAM sizes and partitioning
  • Cache sizes

Different IoT applications have different requirements, but a very common feature is the need to reduce the power consumption. Reducing power consumption is imperative in IoT designs – if this is ignored, the result could be billions of IoT devices wasting energy.

A dual-core system allows the background OS to run on the energy efficient core, while the second high performance core can be turned on for more demanding tasks. This partitioning delivers significant performance bursts while keeping the average power consumption very low.

Caches have also been integrated in the system to reduce power consuming accesses to the Flash, and the always-on domain allows the application to power-off the system while keeping synchronization.

Key benefits

  • Bring an Arm-v8 Cortex-M-based chip to market 6-12 months faster than designing from scratch.
  • The subsystem is pre-integrated and verified to allow you to focus your engineering resource on differentiation.
  • Start development straight away, with Arm mbed™ OS out-of-box software.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

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Not answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 4668 views
Not answered How to handle external blockwise of large files Started 9 hours ago by Alex E 0 replies 35 views
Not answered 2nd noob multiprocessor FVP question, coherency Started 10 hours ago by noway 0 replies 68 views
Suggested answer Noob multiprocessor question for FVP Latest 10 hours ago by noway 2 replies 185 views
Answered Successful flash but program never reaches main() Latest 11 hours ago by t.russell 2 replies 156 views
Suggested answer ARM 8.5-A BTI and MTE Benchmarking Latest 16 hours ago by Stephen Theobald 2 replies 15000 views