Arm Corstone

Build a Secure IoT System on Chip

Arm Corstone provides everything you need to start your SoC design, helping you build SoCs faster and more securely, with the right architecture choice, integration and verification.

At the heart of Corstone is one of the subsystem reference designs. Each one is an implementation of an Arm-defined subsystem architecture. It is a complete solution for architecting the system, making it secure and able to handle the complex power-control infrastructure, while balancing trade-offs between performance and power.

Corstone block diagram

  • Arm has integrated the processor(s), system IP, memory system, debug, security IP and other Arm IP together, simplifying the design process and handling the power control, security and performance in an optimised way.
  • Hundreds of hours of verification work has been dedicated to these subsystems, allowing you to benefit from getting to market quickly.
  • Each subsystem is configurable, modifiable, enabling you to focus on differentiation by customizing the system to meet your unique needs.
  • Corstone has been designed to be extensible so you can build the rest of your SoC on top of the system.
  • Simplify software development with easier porting of open-source Trusted Firmware-M (TF-M) for an accelerated route to PSA Certified.
  • Design confidently with FPGA and Fixed Virtual Prototyping (FVP) platforms based on Corstone. Choose from well supported RTOSs such as as RTX, FreeRTOS, Zephyr and Mbed OS to further reduce software development cost.

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Explore the Corstone packages available for your SoC design.

Component Corstone-101
Corstone-102
Corstone-201
Corstone-300 Corstone-700
Corstone Reference Design Subsystems
SSE-050 Subsystem (Cortex-M3 based)
Yes
Yes  Yes    Yes 
SSE-123 Subsystem (Cortex-M23 based)   Yes
Yes
  Yes
SSE-200 Subsystem (dual Cortex-M33 based)
    Yes
  Yes
SSE-300 Subsystem (Cortex-M55 based)
      Yes
 
SSE-700 Subsystem (Cortex-A32 and Cortex-M based)
        Yes
System IP
CM0SDK and CMSDK (common IP blocks)
Yes
Yes
Yes  Yes
Yes 
True Random Number Generator (TRNG) Real-Time Clock (RTC) Yes
Yes  Yes  Yes
Yes 
CoreLink AHB Flash Cache
Yes
Yes  Yes  Yes
Yes 
CoreLink SIE-200 (AHB5 TrustZone System IP)
  Yes  Yes
Yes
Yes
CoreLink GFC-100 Flash Controller (single port)
Yes  Yes  Yes
Yes
Yes
CoreLink GFC-200 Flash Controller (dual port)
  Yes
Yes
Yes
Yes
CoreLink PCK-600 (power control)
  Yes
Yes
Yes
Yes
CoreLink SDC-600 (authenticated debug)
    Yes
  Yes 
CoreLink LPD-500 (power control)
 
Yes
  Yes
CoreSight SoC-400M (standard debug)
    Yes
 
CoreSight SoC-600 (enhanced debug)
   
  Yes
XHB-500 (AHB5 and AXI bridging IP)
      Yes
Yes 
CoreLink SIE-300 (AXI5 TrustZone System IP)
      Yes

CoreLink NIC-400-Lite
      Yes
 
CoreLink ADB-400
      Yes
 
NIC-450 (network interconnect)
        Yes
CoreSight STM-500 System Trace Macro
        Yes
IntMemAxi (Internal memory interface)
        Yes
UART
        Yes

Corstone-101

Cortex-M0/M0+/M3/M4

Contains a reference design based on the Cortex-M3 as well as all of the fundamental system elements to design an SoC with Cortex-M0, Cortex-M0+ and Cortex-M4 processors.

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Corstone-102

Cortex-M23

Combines all of the necessary hardware elements for an SoC design based& on the Arm Cortex-M23 processor.


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Corstone-201

Cortex-M33

Combines all of the necessary hardware elements for an SoC design based on the Arm Cortex-M33 processor.


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Corstone-300

Cortex-M55

The fastest way to incorporate the AI-capable Cortex-M55 into an SoC design.

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Corstone-700

Cortex-A and Cortex-M

Corstone-700 integrates both Cortex-M and Cortex-A processors in one handy, flexible subsystem. It includes support for system peripherals, plus a broad spectrum of security counter-measures.

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Contact us

Are you looking to grow your IoT portfolio quickly and with minimal risk? Find out how to license processor and Corstone IP through Arm Flexible Access.

Contact us

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Answered IP Camera interface via STM32
  • Cortex-M
  • STM32F
  • Cortex-M4
1 votes 36626 views 8 replies Latest 5 days ago by Akash Kasturi Answer this
Answered spi flash 16MB not working 1 votes 9321 views 2 replies Latest 16 days ago by sridhar6994 Answer this
Answered response ordering at AXI4 slave
  • AXI4
0 votes 2162 views 4 replies Latest 1 months ago by rvora Answer this
Answered Can AHB3_Lite master send an unaligend address?
  • AMBA 4
  • AXI4
  • AHB-Lite
0 votes 1699 views 2 replies Latest 1 months ago by Oliver Beirne Answer this
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY 0 votes 1805 views 3 replies Latest 1 months ago by Oliver Beirne Answer this
Discussion IDE Recommendation
  • Cortex-M3
  • IDEs and Tool Suites
  • Cortex-M
0 votes 6964 views 6 replies Latest 1 months ago by Andy Neil Answer this
Answered IP Camera interface via STM32 Latest 5 days ago by Akash Kasturi 8 replies 36626 views
Answered spi flash 16MB not working Latest 16 days ago by sridhar6994 2 replies 9321 views
Answered response ordering at AXI4 slave Latest 1 months ago by rvora 4 replies 2162 views
Answered Can AHB3_Lite master send an unaligend address? Latest 1 months ago by Oliver Beirne 2 replies 1699 views
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY Latest 1 months ago by Oliver Beirne 3 replies 1805 views
Discussion IDE Recommendation Latest 1 months ago by Andy Neil 6 replies 6964 views