Reference designs for building secure SoCs

The Arm Corstone-102 provides flexible reference design subsystems and system IP for SoC development.

The Arm Corstone-102 combines software and hardware components for Cortex-M-based designs. Based on the Arm Cortex-M23, the Corstone-102 is targeted at the constrained market segment for a typical IoT application.


Features


The Corstone-102 combines the following IP:

Corstone SSE-123 Reference Design Subsystem - The Corstone SSE-123 is an implementation of a Cortex-M23-based subsystem architecture. Integrating components such as interconnects, TrustZone protection controllers, bridges, access control gates, SRAM, APB system peripherals, expansion interfaces, and debug. It also incorporates power domains, clock, and reset control infrastructure. The SSE-123 Example Subsystem is extensible and comes with full modification rights.

The SSE-123 subsystem block diagram.

Corstone SSE-050 Reference Design Subsystem - An efficient and expandable subsystem based on the Cortex-M3 processor.

CoreLink GFC-100 Flash Controller - GFC-100 enables an embedded Flash macro to be integrated easily into any system.

CoreLink GFC-200 Flash Controller - Similar to GFC-100, but the GFC-200 can have access from two masters that can operate in separate domains, such as a Non-secure domain and a Secure domain.

Cortex-M System Design Kit
The Cortex-M System Design Kit (CMSDK) includes many components, such as the multi-layer AHB generator, bridges, adapters, and controllers. The CMSDK offers a reliable and efficient way to connect your system. The CMSDK package includes a few system examples to inspire your future design.

AHB Flash Cache
To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.

Real-Time Clock
A Real-Time Clock (RTC) for applications that must maintain a time base, which is likely to be the case for all embedded applications.

True Random Number Generator
The True Random Number Generator (TRNG) is the minimum element that you must integrate into a device to ensure a strong security foundation.

Supporting IP, Software and Tools

Processor IP

The Corstone-101 can be integrated with Cortex-M processors, optimized for cost, and power-efficient microcontrollers.


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Security IP

Easily incorporate more security IP into your SoC to protect your device from software, physical, lifecycle, and communication attacks.

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Cache Controller IP

Improve system performance and power with cache controllers including CoreLink AHB Cache for data and code.

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Arm Development Studio

This features Keil MDK. Keil MDK is for Arm-based microcontrollers and includes all components that you need to create, build, and debug embedded applications.

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Trusted Firmware-M

Trusted Firmware-M (TF-M) provides open-source reference documents, specifications, and APIs of PSA-trusted code for Armv8-M-based microcontrollers.
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RTOS Support

Arm and partners provide RTOS support for several different platforms based on Corstone, including Mbed OS and Zephyr with TF-M.


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Third-party tools

Created by experts in the Arm architecture, partners in development solutions such as IAR and GCC have designed tools to accelerate your SoC design.

FPGA Images and Support

Arm provides a selection of boards for FPGA prototyping, evaluation, and benchmarking on Arm Cortex-based designs or IoT subsystems. Explore the boards available and download the FPGA images.

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Musca Test Chips

Arm development boards, including the Musca test chips are the ideal platform for accelerating the development and reducing the risk of new SoC designs.



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Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

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Answered how to calculate unaligned address for APB? Latest 4 days ago by Colin Campbell 8 replies 11064 views
Answered ARM vs Thumb vs Thumb2 instruction set Latest 1 months ago by Kevin B 2 replies 11438 views
Answered ARM/THUMB instructions that change execution path? Latest 1 months ago by jakebunt 77 replies 67336 views
Answered AMBA 5 CHI Link Layer (L-Credit Return) Latest 1 months ago by Christopher Tory 3 replies 4144 views
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? Latest 1 months ago by Christopher Tory 1 replies 2586 views
Answered strobe Latest 2 months ago by Christopher Tory 3 replies 8515 views