The Corstone-200 Foundation IP offers:
- The fastest secure solution to lead in the IoT market
- A toolkit to build secure embedded systems
- A subsystem and configurable system IP package
This document provides information for hardware or software engineers who want an overview of the functionality in the Corstone-200 foundation IP.
*Note that Corstone-200 foundation IP was formerly named SDK-200.
Request more information
Want more information about the Corstone-200 foundation IP?
About Corstone-200 Foundation IP
The Corstone-200 foundation IP complements Cortex-M processors, including the latest Armv8-M generation. It is composed of a subsystem and system IP, allowing you to get ahead in the development of secure custom SoCs for IoT or embedded applications!
The SSE-200 subsystem included in the Corstone-200 foundation IP is a fantastic foundation to your Cortex-M design. This subsystem is based on the latest Cortex-M33, with Arm TrustZone support. Deep-rooting security at the foundation of your SoC, TrustZone technology is key to all IoT and embedded applications.
Hardware-securing a system means that many filters need to be implemented to protect memories, peripherals, and enforce access rules at a system level. All of this is pre-integrated and ready to use in the SSE-200 subsystem.
In addition to this, you will need software libraries. Arm also provides open-source permissive licenced software examples to help you with the SSE-200 subsystem. Software for SSE-200 is available via multiple options: an Mbed OS port for providing a complete IoT example and Keil MDK pack with bare-metal drivers in a known tool chain environment. This helps you build firmware faster and cheaper for your system. An FPGA implementation of the subsystem can even be downloaded from the Arm website and can be used immediately for prototyping.
Get the latest software status on community.arm.com.
Moreover, the SSE-200 subsystem follows the reference security architecture for Armv8-M processors. This means you are immediately set to participate in a complete ecosystem around security for embedded devices. The other elements of the Corstone-200 foundation IP help you build your system quickly, securely and reliably. Use them to customize your system or to design your architecture from the ground up. The system components are here to help you get there in the most optimal way.
Key elements of Corstone-200 Foundation IP
The elements of the Corstone-200 foundation IP are a super-set of Corstone-100 foundation IP.
- SSE-200 Subsystem – A TrustZone-enabled subsystem with the latest power-management technology, based on Cortex-M33
- SIE-200 System IP – All the components you need to create TrustZone-enabled systems: AHB5 interconnect generator, memory/peripheral protection controllers, bridges, plus much more.
- SSE-050 Subsystem – An efficient and expandable subsystem based on Cortex-M3
- Cortex-M System Design Kit - Which include a multi-layer AHB generator to connect everything in your system in a reliable and efficient way, bridges, adaptors and controllers. Also features a few system examples to inspire your future design.
- AHB Flash Cache – To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.
- RTC – A real-time clock for applications that need to maintain a time base, which is likely to be the case of all embedded applications!
- TRNG – Security cannot be a second thought! The True Random Number Generator is the minimum element that you have to integrate in a device to ensure a strong security foundation.
The Corstone-200 foundation IP is the fastest way to get to secure silicon. Save time, risk and effort and use it in combination with your Cortex-M processor.
Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Open a support case
|Answered||Where do I find presentations and photos from SC'18?||1 votes||805 views||0 replies||Started 4 months ago by John Linford||Answer this|
|Not answered||Breakpoints (S/H) could not be invoked when EL2 return EL1||0 votes||13 views||0 replies||Started 6 hours ago by freshmen||Answer this|
|Suggested answer||Non-secure code calling secure code - Boot Loaders||0 votes||72 views||2 replies||Latest 7 hours ago by vinkot||Answer this|
|Suggested answer||Count Main TLB miss||0 votes||30 views||1 replies||Latest yesterday by Vanhealsing||Answer this|
|Answered||is there a x86 linux distribution for cross compilation for Raspberry Pi?||0 votes||311 views||3 replies||Latest yesterday by Przemyslaw Wirkus||Answer this|
|Suggested answer||Startup file uvision v5.26||0 votes||122 views||2 replies||Latest yesterday by ctarakci||Answer this|
|Answered||Where do I find presentations and photos from SC'18? Started 4 months ago by John Linford||0 replies 805 views|
|Not answered||Breakpoints (S/H) could not be invoked when EL2 return EL1 Started 6 hours ago by freshmen||0 replies 13 views|
|Suggested answer||Non-secure code calling secure code - Boot Loaders Latest 7 hours ago by vinkot||2 replies 72 views|
|Suggested answer||Count Main TLB miss Latest yesterday by Vanhealsing||1 replies 30 views|
|Answered||is there a x86 linux distribution for cross compilation for Raspberry Pi? Latest yesterday by Przemyslaw Wirkus||3 replies 311 views|
|Suggested answer||Startup file uvision v5.26 Latest yesterday by ctarakci||2 replies 122 views|