Corstone-201 Foundation IP

Corstone foundation IP diagram.

The Corstone-201 Foundation IP offers:

  • A number of secure subsystems to build upon or use as a reference
  • Security at the heart of your SoC
  • A toolkit of system IP to build secure embedded systems

The Corstone-201 offers the perfect starting point for your SoC. The different subsystems that are included can be built upon or used as a reference, leading to a faster time to market and building trust into the heart of your SoC. The Corstone-201 is also a cost effective way to gain access to many of the latest System IP from Arm.

Technical Overview

This document provides information for hardware or software engineers who want an overview of the functionality in the Corstone-201 foundation IP.

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About Corstone-201 Foundation IP

The Corstone-201 foundation IP complements Cortex-M processors, including the latest Armv8-M generation. It is a licensable package composed of subsystems and system IP, allowing you to get ahead in the development of secure custom SoCs for IoT or embedded applications!

The SSE-123 example subsystem included in the Corstone-201 foundation IP provides a secure foundation for the heart of your Cortex-M23 based system. Designed to be the lowest cost and power efficient implementation of an Arm TrustZone system, it is targeted at the constrained market segment. TrustZone technology is key to achieving software isolation of your secure area from the rest of the system. In order to achieve this system wide, many filters need to be in place to protect memories, peripherals and enforce access rules at a system level.

The Corstone-201 also includes the well-established SSE-200 subsystem based on the latest Cortex-M33, with Arm TrustZone support. In addition to this you also get the legacy SSE-050 subsystem based on the Cortex-M3.

Software for these subsystems are mainly provided though open source. For example, an Mbed OS port for the Musca test chip based on the SSE-200 is available. It is also the golden reference for Trusted Firmware-M development as well as support with Keil MDK packs with bare-metal drivers in a known tool chain environment.

Get the latest software status on community.arm.com.

Moreover, the SSE-123 and SSE-200 subsystems follow the reference security architecture for Armv8-M processors. This means you are immediately set to participate in a complete ecosystem around security for embedded devices. The other elements of the Corstone-201 foundation IP help you build your system quickly, securely and reliably. Use them to customize your system or to design your architecture from the ground up. The system components are here to help you get there in the most optimal way.

Key elements of Corstone-201 Foundation IP

The elements of the Corstone-201 foundation IP are a super-set of Corstone-200 foundation IP.

  • SSE-200 Subsystem – A TrustZone-enabled subsystem with the latest power-management technology, based on Cortex-M33.
  • SSE-123 Example Subsystem – A TrustZone-enabled subsystem with the latest power-management technology, based on Cortex-M23.
  • CoreLink SIE-200 System IP – All the components you need to create TrustZone-enabled systems: AHB5 interconnect generator, memory/peripheral protection controllers, bridges, plus much more.
  • SSE-050 Subsystem – An efficient and expandable subsystem based on Cortex-M3.
  • GFC-100 Flash Controller - GFC-100 enables an embedded Flash macro to be integrated easily into any system.
  • GFC-200 Flash Controller – Similar to GFC-100 however the GFC-200 can have accesses from two masters that can operate in separate domains such as a Non- secure domain and a Secure domain.
  • CoreLink PCK-600 Power Control - The Arm CoreLink PCK-600 Power Control Kit provides a suite of system IP that is pre-verified to ease system power and clock management infrastructure integration.
  • CoreSight SDC-600 - CoreSight SDC-600 addresses device security needs by allowing silicon and tool vendors to enforce protection and to police debug access, and by working closely with cryptographic elements and debug certificate authentication.
  • Cortex-M System Design Kit - Which include a multi-layer AHB generator to connect everything in your system in a reliable and efficient way, bridges, adaptors and controllers. Also features a few system examples to inspire your future design.
  • AHB Flash Cache – To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.
  • RTC – A real-time clock for applications that need to maintain a time base, which is likely to be the case for all embedded applications!
  • TRNG – Security cannot be a second thought! The True Random Number Generator is the minimum element that you have to integrate in a device to ensure a strong security foundation.

The Corstone-201 foundation IP is the fastest way to get to secure silicon. Save time, risk and effort and use it in combination with your Cortex-M processor.

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Suggested answer ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state? Latest 6 hours ago by 42Bastian Schick 1 replies 24 views
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